公开(公告)号：US20230238291A1

公开(公告)日：2023-07-27

申请号：US17736549

申请日：2022-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shuqian Huang ,  Sheng Zou ,  Yuchen Li ,  Peng Li ,  Chao Zhuang ,  Zhiyun Liu

IPC: H01L21/66 ,  G05B19/418

CPC classification number: H01L22/20 ,  G05B19/4185 ,  G05B2219/40066

Abstract: The present disclosure generally relates to determining a process condition in a semiconductor process using attribute-relative process conditions. An example is a method of forming an integrated circuit (IC). First and second historical process conditions are obtained. The first historical process conditions are of previous semiconductor processing corresponding to a target value of a process attribute for forming the IC, and the second historical process conditions are of previous semiconductor processing corresponding to variable values of the process attribute. Attribute-relative process conditions are calculated. Each attribute-relative process condition is based on the first historical process conditions and the second historical process conditions that correspond to a respective given value of the variable values. An average process condition is determined from a subset of the attribute-relative process conditions. A process condition of a subsequent semiconductor process is set based on the average process condition.

公开(公告)号：US11417736B2

公开(公告)日：2022-08-16

申请号：US17167911

申请日：2021-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Peng Li ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Jing Hu ,  Chao Zhuang

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.

公开(公告)号：US20240429290A1

公开(公告)日：2024-12-26

申请号：US18751877

申请日：2024-06-24

Applicant: Texas Instruments Incorporated

Inventor： Ya Ping Chen ,  Yunlong Liu ,  Hong Yang ,  Jing Hu ,  Chao Zhuang ,  Peng Li ,  Sheng Pin Yang

IPC: H01L29/40 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes etching a first trench and a second trench in an epitaxial layer over a semiconductor and forming a dielectric liner within the trenches. A photoresist layer is formed within the trenches and over the epitaxial layer and given a post-exposure bake at a first temperature. The photoresist layer is then given an adhesion-promoting bake at a greater second temperature; The photoresist layer is then removed from a top portion the trenches, thereby exposing a top portion of the dielectric liner and leaving a remaining portion of the photoresist in a bottom portion of the trenches. The exposed dielectric liner is etched, thereby leaving a remaining portion of the dielectric liner in the top portion of the trenches. The remaining portion of the photoresist is removed and the trenches are filled with a polysilicon layer.

公开(公告)号：US20220093754A1

公开(公告)日：2022-03-24

申请号：US17167911

申请日：2021-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Peng Li ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Jing Hu ,  Chao Zhuang

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.