公开(公告)号：US11417736B2

公开(公告)日：2022-08-16

申请号：US17167911

申请日：2021-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Peng Li ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Jing Hu ,  Chao Zhuang

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.

公开(公告)号：US20220406885A1

公开(公告)日：2022-12-22

申请号：US17489199

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： Jing Hu ,  Zhi Peng Feng ,  Chao Zuo ,  Dongsheng Liu ,  Yunlong Liu ,  Manoj K. Jain ,  Shengpin Yang

IPC: H01L49/02

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

公开(公告)号：US20240120368A1

公开(公告)日：2024-04-11

申请号：US18543769

申请日：2023-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jing Hu ,  ZHI PENG Feng ,  Chao Zuo ,  Dongsheng Liu ,  Yunlong Liu ,  Manoj K Jain ,  Shengpin Yang

IPC: H01G4/224 ,  H01L21/225 ,  H01L21/3215 ,  H01L21/324 ,  H01L21/74 ,  H01L21/762 ,  H01L29/94

CPC classification number: H01L28/87 ,  H01L21/2253 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/743 ,  H01L21/76237 ,  H01L28/40 ,  H01L29/945

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

公开(公告)号：US20240429290A1

公开(公告)日：2024-12-26

申请号：US18751877

申请日：2024-06-24

Applicant: Texas Instruments Incorporated

Inventor： Ya Ping Chen ,  Yunlong Liu ,  Hong Yang ,  Jing Hu ,  Chao Zhuang ,  Peng Li ,  Sheng Pin Yang

IPC: H01L29/40 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes etching a first trench and a second trench in an epitaxial layer over a semiconductor and forming a dielectric liner within the trenches. A photoresist layer is formed within the trenches and over the epitaxial layer and given a post-exposure bake at a first temperature. The photoresist layer is then given an adhesion-promoting bake at a greater second temperature; The photoresist layer is then removed from a top portion the trenches, thereby exposing a top portion of the dielectric liner and leaving a remaining portion of the photoresist in a bottom portion of the trenches. The exposed dielectric liner is etched, thereby leaving a remaining portion of the dielectric liner in the top portion of the trenches. The remaining portion of the photoresist is removed and the trenches are filled with a polysilicon layer.

公开(公告)号：US20240258112A1

公开(公告)日：2024-08-01

申请号：US18103134

申请日：2023-01-30

Applicant: Texas Instruments Incorporated

Inventor： Chao Zuo ,  Jing Hu ,  Tian Ping Lv ,  Abbas Ali ,  Manoj K Jain

IPC: H01L21/3065

CPC classification number: H01L21/30655 ,  H01L28/40

Abstract: A method of forming an integrated circuit includes forming a plurality of openings in a resist layer over a semiconductor substrate and removing portions of a semiconductor surface layer exposed by the openings, thereby forming a plurality of deep trenches. Removing the portions includes performing a first etch loop for a first plurality of repetitions, the first etch loop including a deposition process executed for a first deposition time and an etch process executed for a first etch time. The removing further includes performing a second etch loop for a second plurality of repetitions, the second etch loop including the deposition process executed for a second deposition time and an etch process executed for a second etch time. The second deposition time is at least 10% greater than the first deposition time, and the second etch time is at least 10% greater than the first etch time.

公开(公告)号：US11888021B2

公开(公告)日：2024-01-30

申请号：US17489199

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： Jing Hu ,  Zhi Peng Feng ,  Chao Zuo ,  Dongsheng Liu ,  Yunlong Liu ,  Manoj K Jain ,  Shengpin Yang

IPC: H01L21/762 ,  H01L49/02 ,  H01L21/324 ,  H01L21/225 ,  H01L21/74 ,  H01L29/94 ,  H01L21/3215

CPC classification number: H01L28/87 ,  H01L21/2253 ,  H01L21/324 ,  H01L21/32155 ,  H01L21/743 ,  H01L21/76237 ,  H01L28/40 ,  H01L29/945

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

公开(公告)号：US20220093754A1

公开(公告)日：2022-03-24

申请号：US17167911

申请日：2021-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Peng Li ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Jing Hu ,  Chao Zhuang

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.