公开(公告)号：US20190296115A1

公开(公告)日：2019-09-26

申请号：US16042834

申请日：2018-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ya ping Chen ,  Hong Yang ,  Peng Li ,  Seetharaman Sridhar ,  Yunlong Liu ,  Rui Liu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.

公开(公告)号：US11417736B2

公开(公告)日：2022-08-16

申请号：US17167911

申请日：2021-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Peng Li ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Jing Hu ,  Chao Zhuang

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.

公开(公告)号：US11322594B2

公开(公告)日：2022-05-03

申请号：US17134706

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Fei Ma ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Baoqiang Niu ,  Rui Liu ,  Zhi Peng Feng ,  Seetharaman Sridhar ,  Sunglyong Kim

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/765 ,  H01L29/423 ,  H01L27/24 ,  H01L21/8234

Abstract: A semiconductor device, and methods of forming the same. In one example, the semiconductor device includes a trench in a substrate having a top surface, and a shield within the trench. The semiconductor device also includes a shield liner between a sidewall of the trench and the shield, and a lateral insulator over the shield contacting the shield liner. The semiconductor device also includes a gate dielectric layer on an exposed sidewall of the trench between the lateral insulator and the top surface. The lateral insulator may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer.

公开(公告)号：US20230087151A1

公开(公告)日：2023-03-23

申请号：US17502692

申请日：2021-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Grebs ,  Meng-Chia Lee ,  Hong Yang ,  Ya ping Chen ,  Sunglyong Kim

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A trench gate metal oxide semiconductor (MOSFET) device includes a substrate with a semiconductor surface layer doped a first conductivity type. At least one trench gate MOSFET cell is located in or over the semiconductor surface layer, and includes a body region in the semiconductor surface layer doped a second conductivity type, and a source region on top of the body region doped the first conductivity type. A trench extends down from a top side of the semiconductor surface layer, the trench abutting the body region and being lined with a dielectric material. A field plate that includes polysilicon is located in the trench, and a gate electrode is located over the field plate. The field plate has a bottom portion, a middle portion, and a top portion, wherein the bottom portion is narrower than the middle portion, and the middle portion is narrower than the top portion.

公开(公告)号：US20220093754A1

公开(公告)日：2022-03-24

申请号：US17167911

申请日：2021-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Peng Li ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Jing Hu ,  Chao Zhuang

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.

公开(公告)号：US11791198B2

公开(公告)日：2023-10-17

申请号：US17695119

申请日：2022-03-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hong Yang ,  Seetharaman Sridhar ,  Ya ping Chen ,  Fei Ma ,  Yunlong Liu ,  Sunglyong Kim

IPC: H01L21/762 ,  H01L21/763 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/76235 ,  H01L21/02164 ,  H01L21/308 ,  H01L21/324 ,  H01L21/763 ,  H01L21/76283 ,  H01L21/76286 ,  H01L29/66666

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

公开(公告)号：US11302568B2

公开(公告)日：2022-04-12

申请号：US16546499

申请日：2019-08-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hong Yang ,  Seetharaman Sridhar ,  Ya ping Chen ,  Fei Ma ,  Yunlong Liu ,  Sunglyong Kim

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/308 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

公开(公告)号：US20200335589A1

公开(公告)日：2020-10-22

申请号：US16918130

申请日：2020-07-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ya ping Chen ,  Hong Yang ,  Peng Li ,  Seetharaman Sridhar ,  Yunlong Liu ,  Rui Liu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.

公开(公告)号：US10720499B2

公开(公告)日：2020-07-21

申请号：US16042834

申请日：2018-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ya ping Chen ,  Hong Yang ,  Peng Li ,  Seetharaman Sridhar ,  Yunlong Liu ,  Rui Liu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

Abstract: A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.