公开(公告)号：US10366987B2

公开(公告)日：2019-07-30

申请号：US15211450

申请日：2016-07-15

Applicant: Texas Instruments Incorporated

Inventor： David J. Baldwin ,  Hector X. Roman ,  Md. Abidur Rahman

IPC: H01L27/088 ,  G01R19/00 ,  H03K17/08 ,  H03K17/14 ,  H01L29/78

Abstract: Described example embodiments include an integrated circuit having a first channel area with a first FET formed in a semiconductor substrate, the substrate providing a contact to the drain. A second channel area includes a second FET formed in the semiconductor substrate. A pilot FET couples to the first FET in a current mirror configuration. A third FET has a conductivity opposite the first and second FETs and couples to the source of the pilot FET. An op amp includes an output coupled to the gate of the third FET. Signals from the drain of the second FET and the source of the pilot FET couple to the inverting input of the op amp. Signals from the source of the first FET and the drain of the first FET couple to the non-inverting input of the op amp. Methods and additional apparatus are disclosed.

公开(公告)号：US20170030948A1

公开(公告)日：2017-02-02

申请号：US15211450

申请日：2016-07-15

Applicant: Texas Instruments Incorporated

Inventor： David J. Baldwin ,  Hector X. Roman ,  Md. Abidur Rahman

IPC: G01R19/10 ,  H01L29/417 ,  H01L27/088

CPC classification number: H01L27/088 ,  G01R19/0092 ,  H01L29/7802 ,  H03K17/08 ,  H03K17/145

Abstract: Described example embodiments include an integrated circuit having a first channel area with a first FET formed in a semiconductor substrate, the substrate providing a contact to the drain. A second channel area includes a second FET formed in the semiconductor substrate. A pilot FET couples to the first FET in a current mirror configuration. A third FET has a conductivity opposite the first and second FETs and couples to the source of the pilot FET. An op amp includes an output coupled to the gate of the third FET. Signals from the drain of the second FET and the source of the pilot FET couple to the inverting input of the op amp. Signals from the source of the first FET and the drain of the first FET couple to the non-inverting input of the op amp. Methods and additional apparatus are disclosed.

Abstract translation: 所描述的示例实施例包括具有形成在半导体衬底中的第一FET的第一沟道区的集成电路，该衬底提供与漏极的接触。 第二沟道区域包括形成在半导体衬底中的第二FET。 引导FET以电流镜配置耦合到第一FET。 第三FET具有与第一和第二FET相反的导电性并耦合到引导FET的源极。 运算放大器包括耦合到第三FET的栅极的输出。 来自第二FET的漏极和引导FET的源极的信号耦合到运算放大器的反相输入。 来自第一FET的源极和第一FET耦合的漏极到运算放大器的非反相输入端的信号。 公开了方法和附加装置。