公开(公告)号：US12107127B2

公开(公告)日：2024-10-01

申请号：US17690374

申请日：2022-03-09

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

发明人： Hiroshi Kono ,  Teruyuki Ohashi ,  Takahiro Ogata

IPC分类号： H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/1608 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7802

摘要： A semiconductor device of embodiments includes: a first electrode; a second electrode; a gate electrode extending in a first direction; and a SiC layer. The SiC layer includes: a first conductive type first SiC region having a first region, a second region facing the gate electrode, and a third region in contact with the first electrode; a second conductive type second SiC region between the second region and the third region; a second conductive type third SiC region, the second region interposed between the second SiC region and the third SiC region; a second conductive type fourth SiC region, the third region interposed between the second SiC region and the fourth SiC region; a first conductive type fifth SiC region; a second conductive type sixth SiC region between the first region and the second SiC region; and a second conductive type seventh SiC region between the first region and the second SiC region and distant from the sixth SiC region in the first direction.

公开(公告)号：US20240321970A1

公开(公告)日：2024-09-26

申请号：US18734613

申请日：2024-06-05

申请人： ROHM CO., LTD.

发明人： Takuji MAEKAWA ,  Mitsuru MORIMOTO

IPC分类号： H01L29/16 ,  H01L21/02 ,  H01L29/04 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872

CPC分类号： H01L29/1608 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02516 ,  H01L21/02529 ,  H01L21/02595 ,  H01L29/045 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/872

摘要： A semiconductor substrate includes a drift layer of a first layer formed of a single crystal SiC semiconductor and a buffer layer and a substrate layer of a second layer that is formed of a SiC semiconductor which includes a polycrystalline structure and is formed on the surface of the first layer, in which the second layer (12) is formed on the surface of the drift layer of the first layer by means of CVD growth, the drift layer of the first layer is formed by means of epitaxial growth, and accordingly, defects occurring at a junction interface of the semiconductor substrate including the single crystal SiC layer and the polycrystal SiC layer are suppressed, and manufacturing costs are also reduced.

公开(公告)号：US20240321592A1

公开(公告)日：2024-09-26

申请号：US18731643

申请日：2024-06-03

申请人： FLOSFIA INC.

发明人： Isao TAKAHASHI

IPC分类号： H01L21/465 ,  H01L21/67 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872

CPC分类号： H01L21/465 ,  H01L21/6708 ,  H01L29/66969 ,  H01L29/7802 ,  H01L29/872

摘要： In a first aspect of a present inventive subject matter, a method of etching includes etching an object at a temperature that is higher than 200° C. with atomized droplets of an etching liquid.

公开(公告)号：US20240297220A1

公开(公告)日：2024-09-05

申请号：US18236925

申请日：2023-08-22

申请人： Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

发明人： Masatsugu NAGAI ,  Shingo SATO

IPC分类号： H01L29/08 ,  H01L21/265 ,  H01L21/285 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0856 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/66712 ,  H01L29/7802

摘要： A semiconductor device includes a semiconductor layer, first and second electrodes, a control electrode, and a connection region. The semiconductor layer includes first to third semiconductor regions. The connection region is positioned between the first electrode and the first semiconductor region. The connection region includes a compound of a first metallic element and Si, and a compound of Pt and Si. The first metallic element is at least one selected from the group consisting of Ti, V, Cr, Zr, Mo, Hf, Ta, and W. The connection region includes a first part adjacent to an n-type region of the semiconductor layer in a first direction. A peak position of a concentration distribution of the first metallic element in the first direction of the first part is between the n-type region and a peak position of a concentration distribution of Pt in the first direction of the first part.

公开(公告)号：US20240266400A1

公开(公告)日：2024-08-08

申请号：US18365681

申请日：2023-08-04

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Johji NISHIO ,  Tatsuo SHIMIZU ,  Chiharu OTA ,  Ryosuke IIJIMA

IPC分类号： H01L29/10 ,  H01L21/04 ,  H01L29/16 ,  H01L29/78

CPC分类号： H01L29/1095 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/7802

摘要： According to one embodiment, a semiconductor device includes a base, a first silicon carbide region, and a second silicon carbide region. The first silicon carbide region includes at least one selected from the group consisting of nitrogen, phosphorus and arsenic. The second silicon carbide region includes at least one selected from the group consisting of boron, aluminum and gallium. The first silicon carbide region is provided between the base and the second silicon carbide region. At least a part of the first silicon carbide region includes fluorine.

公开(公告)号：US20240234508A9

公开(公告)日：2024-07-11

申请号：US18162816

申请日：2023-02-01

申请人： TRinno Technology Co., Ltd.

发明人： Kwang Hoon OH ,  Jin Young Jung ,  Soo Seong Kim

IPC分类号： H01L29/16 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1608 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66068 ,  H01L29/7802

摘要： Silicon carbide power semiconductor device having uniform channel length and manufacturing method thereof disclosed. The power semiconductor device includes a drift region of a first conductivity type, a plurality of body regions of a second conductivity type, being formed to be spaced apart from each other with a preset WS in a horizontal direction in an upper region of the drift region, a JFET region of the first conductivity type and a low-resistance region of the first conductivity type, being formed in a separation space between adjacent body regions to contact their side surfaces with the adjacent body regions and a source region of the first conductivity type, being formed in a surface region in the body region in contact with the low-resistance region to be spaced apart from the low-resistance region by a preset channel length.

公开(公告)号：US12014924B2

公开(公告)日：2024-06-18

申请号：US17258967

申请日：2019-06-14

申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

发明人： Kenji Kanbara ,  Hironori Itoh ,  Tsutomu Hori

IPC分类号： H01L29/36 ,  C30B29/36 ,  H01L21/02 ,  H01L21/04 ,  H01L21/78 ,  H01L29/16 ,  H01L29/34 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/02529 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/046 ,  H01L21/78 ,  H01L29/1608 ,  H01L29/34 ,  H01L29/66068 ,  H01L29/7802

摘要： When a value obtained by dividing the number of the one or more second regions by a total of the number of the one or more first regions and the number of the one or more second regions is defined as a first defect free area ratio, a value obtained by dividing the number of the one or more fourth regions by a total of the number of the one or more third regions and the number of the one or more fourth regions is defined as a second defect free area ratio, and a value obtained by dividing the number of the one or more macroscopic defects by an area of the central region is defined as X cm−2, A is smaller than B, B is less than or equal to 4, X is more than 0 and less than 4, and a Formula 1 is satisfied.

公开(公告)号：US12009419B2

公开(公告)日：2024-06-11

申请号：US17569284

申请日：2022-01-05

申请人： DB HiTek Co., Ltd.

发明人： Yong Sin Han ,  Myeong Bum Pyun

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739

CPC分类号： H01L29/7802 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/42368

摘要： Disclosed are a superjunction semiconductor device and a method of manufacturing the same. More particularly, the present disclosure relates to a superjunction semiconductor device and a method of manufacturing the same, in which the device includes a field oxide layer having an uppermost end or surface that is higher than that of a gate oxide layer, between a gate electrode and a second pillar region in a cell region. This enables a reduction in gate-drain parasitic capacitance, thereby increasing switching speed and reducing switching loss.

公开(公告)号：US11990542B2

公开(公告)日：2024-05-21

申请号：US17414253

申请日：2019-11-25

申请人： PANASONIC CORPORATION

发明人： Daisuke Shibata ,  Satoshi Tamura ,  Masahiro Ogawa

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/78

CPC分类号： H01L29/7788 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7789 ,  H01L29/7802

摘要： A nitride semiconductor device includes: a substrate; an n-type drift layer; a p-type blocking layer; a gate opening which penetrates through the blocking layer to the drift layer; an electron transport layer and an electron supply layer provided on an inner face of the gate opening; a gate electrode above the electron supply layer and covering the gate opening; a source opening penetrating through the electron supply layer and the electron transport layer to the blocking layer; a source electrode covering the source opening, the source electrode being connected to the electron supply layer, the electron transport layer, and the blocking layer; and a drain electrode on a side of the substrate opposite from a side on which the blocking layer is located. A bottom face of the gate electrode is closer to the drain electrode than a bottom face of the blocking layer is.

公开(公告)号：US20240162343A1

公开(公告)日：2024-05-16

申请号：US18452805

申请日：2023-08-21

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Yuji ENARI ,  Takashi TONEGAWA

IPC分类号： H01L29/78 ,  H01L23/00 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7802 ,  H01L24/05 ,  H01L24/06 ,  H01L29/1095 ,  H01L29/66712 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05557 ,  H01L2224/05561 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2924/13091

摘要： An interlayer insulating film is formed on an upper surface of a semiconductor substrate. A source pad and a kelvin pad, a gate pad, and a drain pad each having a smaller plane area than a plane area of the source pad are formed on the interlayer insulating film. A first plating layer is formed on the source pad. A second plating layer is formed on each of the kelvin pad, the gate pad, and the drain pad. A material of an uppermost surface of the first plating layer is a metal other than a noble metal, and a material of an uppermost surface of the second plating layer is a noble metal.