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1.发明申请Non-volatile memory and manufacturing method using STI trench implantation 有权使用STI沟槽植入的非易失性存储器和制造方法公开(公告)号：US20050101102A1
公开(公告)日：2005-05-12
申请号：US10703289
申请日：2003-11-06
申请人： Tze Ho Chan , Weining Li , Elgin Quek , Jia Zheng , Pradeep Ramachandramurthy Yelehanka , Tommy Lai
发明人： Tze Ho Chan , Weining Li , Elgin Quek , Jia Zheng , Pradeep Ramachandramurthy Yelehanka , Tommy Lai
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8247 , H01L27/115 , H01L21/76
CPC分类号： H01L27/11521 , H01L21/76237 , H01L27/115 , H01L29/66825
摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.
摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底中形成两个沟槽以在其间限定有源区。 植入的源极区域形成在有源区域的一侧的沟槽中的一个中。 在有源区的另一侧的另一个沟槽中形成注入的漏极区。 然后在沟槽中形成浅沟槽隔离。 在有源区域上形成一个或多个栅极，并且形成与注入源极区域和注入的漏极区域的接触。
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公开(公告)号：US20050026337A1
公开(公告)日：2005-02-03
申请号：US10628912
申请日：2003-07-28
IPC分类号： H01L21/332 , H01L21/8244 , H01L27/11
CPC分类号： H01L29/66393 , H01L27/11
摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P—N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.
摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在其上形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 至少两层是水平形成的，并且至少两层是垂直形成的。 在至少一个垂直形成的层之间形成栅极。 在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。
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公开(公告)号：US20050098794A1
公开(公告)日：2005-05-12
申请号：US11009772
申请日：2004-12-11
IPC分类号： H01L21/332 , H01L21/8244 , H01L27/11 , H01L29/423
CPC分类号： H01L29/66393 , H01L27/11
摘要： An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.
摘要翻译： 集成电路结构包括形成在其上的半导体衬底和晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 至少两层是水平形成的，并且至少两层是垂直形成的。 在至少一个垂直形成的层之间形成栅极。 在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。
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4.发明授权公开(公告)号：US08236646B2
公开(公告)日：2012-08-07
申请号：US10703289
申请日：2003-11-06
申请人： Tze Ho Simon Chan , Weining Li , Elgin Quek , Jia Zhen Zheng , Pradeep Ramachandramurthy Yelehanka , Tommy Lai
发明人： Tze Ho Simon Chan , Weining Li , Elgin Quek , Jia Zhen Zheng , Pradeep Ramachandramurthy Yelehanka , Tommy Lai
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/76237 , H01L27/115 , H01L29/66825
摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.
摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底中形成两个沟槽以在其间限定有源区。 植入的源极区域形成在有源区域的一侧的沟槽中的一个中。 在有源区的另一侧的另一个沟槽中形成注入的漏极区。 然后在沟槽中形成浅沟槽隔离。 在有源区域上形成一个或多个栅极，并且形成与注入源极区域和注入的漏极区域的接触。
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公开(公告)号：US06849481B1
公开(公告)日：2005-02-01
申请号：US10628912
申请日：2003-07-28
IPC分类号： H01L21/332 , H01L21/8244 , H01L27/11
CPC分类号： H01L29/66393 , H01L27/11
摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.
摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在其上形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 至少两层是水平形成的，并且至少两层是垂直形成的。 在至少一个垂直形成的层之间形成栅极。 在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。
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公开(公告)号：US07148522B2
公开(公告)日：2006-12-12
申请号：US11009772
申请日：2004-12-11
IPC分类号： H01L29/78
CPC分类号： H01L29/66393 , H01L27/11
摘要： An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.
摘要翻译： 集成电路结构包括形成在其上的半导体衬底和晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 至少两层是水平形成的，并且至少两层是垂直形成的。 在至少一个垂直形成的层之间形成栅极。 在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。
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7.发明申请Integrated circuit with protected implantation profiles and method for the formation thereof 有权具有保护注入轮廓的集成电路及其形成方法公开(公告)号：US20050085056A1
公开(公告)日：2005-04-21
申请号：US10689923
申请日：2003-10-17
IPC分类号： H01L21/3115 , H01L21/314 , H01L21/8239 , H01L21/8247 , H01L21/425 , H01L21/336 , H01L21/31 , H01L21/469
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/31155 , H01L21/3144 , H01L27/1052 , H01L27/11546
摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.
摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底上形成至少一个氧化物 - 氮化物 - 氧化物电介质层。 在形成氧化物 - 氮化物 - 氧化物电介质层之后，至少一个注入形成在氧化物 - 氮化物 - 氧化物介电层下方的半导体衬底的至少一个区域中。
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8.发明授权Integrated circuit with protected implantation profiles and method for the formation thereof 有权具有保护注入轮廓的集成电路及其形成方法公开(公告)号：US07067362B2
公开(公告)日：2006-06-27
申请号：US10689923
申请日：2003-10-17
IPC分类号： H01L21/337
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/31155 , H01L21/3144 , H01L27/1052 , H01L27/11546
摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.
摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底上形成至少一个氧化物 - 氮化物 - 氧化物电介质层。 在形成氧化物 - 氮化物 - 氧化物电介质层之后，至少一个注入形成在氧化物 - 氮化物 - 氧化物介电层下方的半导体衬底的至少一个区域中。
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9.发明授权Integrated circuit with protected implantation profiles and method for the formation thereof 有权具有保护注入轮廓的集成电路及其形成方法公开(公告)号：US07501683B2
公开(公告)日：2009-03-10
申请号：US11421047
申请日：2006-05-30
IPC分类号： H01L29/792
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/31155 , H01L21/3144 , H01L27/1052 , H01L27/11546
摘要： An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.
摘要翻译： 集成电路结构包括提供半导体衬底并在半导体衬底上形成至少一个氧化物 - 氮化物 - 氧化物电介质层。 在形成氧化物 - 氮化物 - 氧化物电介质层之后，至少一个注入形成在氧化物 - 氮化物 - 氧化物介电层下方的半导体衬底的至少一个区域中。
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公开(公告)号：US20050148118A1
公开(公告)日：2005-07-07
申请号：US10752357
申请日：2004-01-05
IPC分类号： H01L21/332 , H01L21/8244 , H01L27/06 , H01L27/11 , H01L29/74
CPC分类号： H01L27/11 , H01L27/0617 , H01L29/66393 , H01L29/7436
摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.
摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在其中形成沟槽。 在沟槽周围和半导体衬底内形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 晶闸管的栅极形成在沟槽内。 在半导体衬底上形成存取晶体管。 在晶闸管和存取晶体管之间形成互连。
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