公开(公告)号：US20240347621A1

公开(公告)日：2024-10-17

申请号：US18755727

申请日：2024-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Ming-Chang Lu

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/778

Abstract: A high electron mobility transistor includes a substrate. A first III-V compound layer is disposed on the substrate. A second III-V compound layer is embedded within the first III-V compound layer. A P-type gallium nitride gate is embedded within the second Ill-V compound layer. A gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate. A source electrode is disposed at one side of the gate electrode. A drain electrode is disposed at another side of the gate electrode.

公开(公告)号：US20210242018A1

公开(公告)日：2021-08-05

申请号：US17218112

申请日：2021-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Hon-Huei Liu ,  Ming-Chang Lu ,  Chin-Fu Lin ,  Yu-Cheng Tung

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L23/00

Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.

公开(公告)号：US10861970B1

公开(公告)日：2020-12-08

申请号：US16596773

申请日：2019-10-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Chun-Liang Hou ,  Wen-Jung Liao ,  Ming-Chang Lu

IPC: H01L29/20 ,  H01L29/78 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor epitaxial structure with reduced defects, including a substrate with a recess formed thereon, an island insulator on a bottom surface of the recess, spacers on sidewalls of the recess, a buffer layer in the recess and covering the island insulator, a channel layer in the recess and on the buffer layer, and a barrier layer in the recess and on the channel layer, wherein two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) is formed in the channel layer.

公开(公告)号：US11011376B2

公开(公告)日：2021-05-18

申请号：US16242994

申请日：2019-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Hon-Huei Liu ,  Ming-Chang Lu ,  Chin-Fu Lin ,  Yu-Cheng Tung

IPC: H01L21/76 ,  H01L21/02 ,  H01L29/20 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L23/00

Abstract: The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same. The semiconductor structure with the epitaxial layer includes a substrate, a blocking layer on the substrate, multiple recesses formed in the substrate, wherein the recess extends along crystal faces of the substrate, and an epitaxial layer on the blocking layer, wherein the epitaxial layer is provided with a buried portion in each recess and an above-surface portion formed on the blocking layer.

公开(公告)号：US10290710B2

公开(公告)日：2019-05-14

申请号：US15696167

申请日：2017-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Ming-Chang Lu ,  Wei Chen ,  Hui-Lin Wang ,  Yi-Ting Liao ,  Chin-Fu Lin

IPC: H01L29/10 ,  H01L21/385 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.

公开(公告)号：US10283614B1

公开(公告)日：2019-05-07

申请号：US15886724

申请日：2018-02-01

Applicant: United Microelectronics Corp.

Inventor： Ming-Chang Lu ,  Wei Chen

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/20 ,  H01L29/267 ,  H01L21/02 ,  H01L29/43 ,  H01L29/778 ,  H01L29/417

Abstract: Provided is a semiconductor structure including a substrate, a first semiconductor layer, a second semiconductor layer, a gate electrode, a source electrode and a drain electrode. The first semiconductor layer contains a group III-V-VI semiconductor compound layer and is disposed on the substrate. The second semiconductor layer includes a group III-V semiconductor compound and is disposed on the first semiconductor layer. The gate electrode is disposed on the second semiconductor layer. The source electrode and the drain electrode are disposed on the second semiconductor layer beside the gate electrode.

公开(公告)号：US20190074357A1

公开(公告)日：2019-03-07

申请号：US15696167

申请日：2017-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Ming-Chang Lu ,  Wei Chen ,  Hui-Lin Wang ,  Yi-Ting Liao ,  Chin-Fu Lin

IPC: H01L29/10 ,  H01L29/24 ,  H01L29/51 ,  H01L21/385 ,  H01L29/66

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.

公开(公告)号：US20230083904A1

公开(公告)日：2023-03-16

申请号：US17500954

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Ming-Chang Lu

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

Abstract: A high electron mobility transistor includes a substrate. A first III-V compound layer is disposed on the substrate. A second III-V compound layer is embedded within the first III-V compound layer. A P-type gallium nitride gate is embedded within the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate. A source electrode is disposed at one side of the gate electrode. A drain electrode is disposed at another side of the gate electrode.

公开(公告)号：US12057490B2

公开(公告)日：2024-08-06

申请号：US17500954

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Ming-Chang Lu

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/778

Abstract: A high electron mobility transistor includes a substrate. A first III-V compound layer is disposed on the substrate. A second III-V compound layer is embedded within the first III-V compound layer. A P-type gallium nitride gate is embedded within the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate. A source electrode is disposed at one side of the gate electrode. A drain electrode is disposed at another side of the gate electrode.

公开(公告)号：US11450747B2

公开(公告)日：2022-09-20

申请号：US17218112

申请日：2021-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Hon-Huei Liu ,  Ming-Chang Lu ,  Chin-Fu Lin ,  Yu-Cheng Tung

IPC: H01L29/04 ,  H01L29/20 ,  H01L21/02 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L23/00 ,  H01L33/00 ,  H01L33/12 ,  H01L33/16 ,  H01L29/165

Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.