公开(公告)号：US20160099184A1

公开(公告)日：2016-04-07

申请号：US14509032

申请日：2014-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Yu-Lin Wang ,  Chun-Chieh Chang ,  Tzu-Feng Chang ,  Po-Peng Lin

IPC: H01L21/66 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/11

CPC classification number: H01L22/14 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/1104

Abstract: A method of estimating the capability of a semiconductor manufacturing system is provided. Plural first transistors are formed and a first VtMM value and a first scale value are obtained. Plural second transistors are formed and a second VtMM value and a second scale value are obtained. Plural third transistors are formed and a third VtMM value and a third scale value are obtained. A first channel length of the first transistor is smaller than a second channel length of the second transistor and is equal to a third channel length of the third transistor. A VtMM v.s. scale figure is established. A line is formed by linking the first dot and the third dot and a vertical Gap between the line and the second dot is measured. The capability of the semiconductor system is determined based on the vertical Gap. The invention further provides a chip.

Abstract translation: 提供了一种估计半导体制造系统的能力的方法。 形成多个第一晶体管，并获得第一VtMM值和第一刻度值。 形成多个第二晶体管，并获得第二VtMM值和第二刻度值。 形成多个第三晶体管，并获得第三VtMM值和第三比例值。 第一晶体管的第一沟道长度小于第二晶体管的第二沟道长度，并且等于第三晶体管的第三沟道长度。 VtMM v.s. 规模建立。 通过连接第一点和第三点形成线，并且测量线与第二点之间的垂直间隙。 基于垂直间隙确定半导体系统的能力。 本发明还提供一种芯片。