公开(公告)号：US20220238158A1

公开(公告)日：2022-07-28

申请号：US17179418

申请日：2021-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng ,  Chun-Chieh Chang

IPC: G11C15/04

Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

公开(公告)号：US11475952B2

公开(公告)日：2022-10-18

申请号：US17179418

申请日：2021-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng ,  Chun-Chieh Chang

IPC: G11C15/04

Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

公开(公告)号：US12224001B2

公开(公告)日：2025-02-11

申请号：US18071658

申请日：2022-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Yu-Fang Chen ,  Chun-Yen Tseng ,  Tzu-Feng Chang ,  Chun-Chieh Chang

IPC: G11C11/412 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

公开(公告)号：US20160099184A1

公开(公告)日：2016-04-07

申请号：US14509032

申请日：2014-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Yu-Lin Wang ,  Chun-Chieh Chang ,  Tzu-Feng Chang ,  Po-Peng Lin

IPC: H01L21/66 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/11

CPC classification number: H01L22/14 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/1104

Abstract: A method of estimating the capability of a semiconductor manufacturing system is provided. Plural first transistors are formed and a first VtMM value and a first scale value are obtained. Plural second transistors are formed and a second VtMM value and a second scale value are obtained. Plural third transistors are formed and a third VtMM value and a third scale value are obtained. A first channel length of the first transistor is smaller than a second channel length of the second transistor and is equal to a third channel length of the third transistor. A VtMM v.s. scale figure is established. A line is formed by linking the first dot and the third dot and a vertical Gap between the line and the second dot is measured. The capability of the semiconductor system is determined based on the vertical Gap. The invention further provides a chip.

Abstract translation: 提供了一种估计半导体制造系统的能力的方法。 形成多个第一晶体管，并获得第一VtMM值和第一刻度值。 形成多个第二晶体管，并获得第二VtMM值和第二刻度值。 形成多个第三晶体管，并获得第三VtMM值和第三比例值。 第一晶体管的第一沟道长度小于第二晶体管的第二沟道长度，并且等于第三晶体管的第三沟道长度。 VtMM v.s. 规模建立。 通过连接第一点和第三点形成线，并且测量线与第二点之间的垂直间隙。 基于垂直间隙确定半导体系统的能力。 本发明还提供一种芯片。

公开(公告)号：US20250095724A1

公开(公告)日：2025-03-20

申请号：US18966047

申请日：2024-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Yu-Fang Chen ,  Chun-Yen Tseng ,  Tzu- Feng Chang ,  Chun-Chieh Chang

IPC: G11C11/412 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

公开(公告)号：US20240161818A1

公开(公告)日：2024-05-16

申请号：US18071658

申请日：2022-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Yu-Fang Chen ,  Chun-Yen Tseng ,  Tzu-Feng Chang ,  Chun-Chieh Chang

IPC: G11C11/412 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: G11C11/412 ,  H01L27/1104 ,  H01L29/6681 ,  H01L29/7851

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.