公开(公告)号：US09871047B1

公开(公告)日：2018-01-16

申请号：US15410933

申请日：2017-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Lin Wang ,  Wei-Chi Lee

IPC: H01L27/11 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/785

Abstract: A semiconductor structure includes a SRAM cell having transistors defined by fins and metal gate stack structures. A transistor and a corresponding pick up cell are disposed in an extension direction of the fins. The transistor and the corresponding pick up cell have metal gate stack structures of the same type.

公开(公告)号：US20170243861A1

公开(公告)日：2017-08-24

申请号：US15088122

申请日：2016-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Tzu-Feng Chang ,  Wei-Chi Lee

IPC: H01L27/02 ,  G03F1/36 ,  G06F17/50 ,  G11C11/419

CPC classification number: H01L27/0207 ,  G03F1/36 ,  G06F17/5068 ,  G11C11/412 ,  G11C11/419 ,  H01L27/1104

Abstract: A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access transistor, a second inner access transistor, a first outer access transistor and a second outer access transistor are electrically connected to the latch circuit, wherein the first outer access transistor has a first gate length, the first inner access transistor has a second gate length, and the first gate length is different from the second gate length.

公开(公告)号：US09721841B1

公开(公告)日：2017-08-01

申请号：US15140019

申请日：2016-04-27

Applicant: United Microelectronics Corp.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Ching-Wen Hung ,  En-Chiuan Liou ,  Chih-Sen Huang

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/088 ,  H01L29/49 ,  H01L29/06

CPC classification number: H01L21/823456 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/4916

Abstract: An electronic circuit includes a plurality of fin lines on a substrate and a plurality of gate lines with a first line width, crossing over the fin lines. The gate lines are parallel and have a plurality of discontinuous regions forming as a plurality of slots. A region of any one of the gate lines adjacent to an unbalance of the slots has a second line width smaller than the first line width.

公开(公告)号：US20150348850A1

公开(公告)日：2015-12-03

申请号：US14289657

申请日：2014-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Yu-Lin Wang ,  Chung-Yuan Lee

IPC: H01L21/8238 ,  G03F1/00

CPC classification number: H01L21/823842 ,  G03F1/00

Abstract: A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.

Abstract translation: 掩模组包括第一掩模和第二掩模。 第一个面具包括几何图案。 第二掩模包括至少带状的图案，其具有第一边缘和与第一边缘相对的第二边缘。 带状图案具有沿着带状图案的长轴的中心线。 第一边缘包括朝向中心线移动的向内移位的段，并且每个向内移位的段与每个几何图案重叠。

公开(公告)号：US20190067268A1

公开(公告)日：2019-02-28

申请号：US16171339

申请日：2018-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Tzu-Feng Chang ,  Wei-Chi Lee

IPC: H01L27/02 ,  G03F1/36 ,  G06F17/50 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11

CPC classification number: H01L27/0207 ,  G03F1/36 ,  G06F17/5068 ,  G11C11/412 ,  G11C11/419 ,  H01L27/1104

Abstract: The present invention provides a layout pattern of a static random access memory (SRAM). The layout pattern includes a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes four transistors, a first access transistor (PG1) and a second access transistor (PG2) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the first access transistor has a second gate length, and the first gate length is different from the second gate length, and two read transistors series connected to each other, wherein one of the two read transistors is connected to the latch circuit.

公开(公告)号：US10396064B2

公开(公告)日：2019-08-27

申请号：US16171339

申请日：2018-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Tzu-Feng Chang ,  Wei-Chi Lee

IPC: H01L27/02 ,  G03F1/36 ,  G06F17/50 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: The present invention provides a layout pattern of a static random access memory (SRAM). The layout pattern includes a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes four transistors, a first access transistor (PG1) and a second access transistor (PG2) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the first access transistor has a second gate length, and the first gate length is different from the second gate length, and two read transistors series connected to each other, wherein one of the two read transistors is connected to the latch circuit.

公开(公告)号：US09455202B2

公开(公告)日：2016-09-27

申请号：US14289657

申请日：2014-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Yu-Lin Wang ,  Chung-Yuan Lee

IPC: H01L21/8238 ,  G03F1/00

CPC classification number: H01L21/823842 ,  G03F1/00

Abstract: A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.

Abstract translation: 掩模组包括第一掩模和第二掩模。 第一个面具包括几何图案。 第二掩模包括至少带状的图案，其具有第一边缘和与第一边缘相对的第二边缘。 带状图案具有沿着带状图案的长轴的中心线。 第一边缘包括朝向中心线移动的向内移位的段，并且每个向内移位的段与每个几何图案重叠。

公开(公告)号：US20160099184A1

公开(公告)日：2016-04-07

申请号：US14509032

申请日：2014-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Yu-Lin Wang ,  Chun-Chieh Chang ,  Tzu-Feng Chang ,  Po-Peng Lin

IPC: H01L21/66 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/11

CPC classification number: H01L22/14 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/1104

Abstract: A method of estimating the capability of a semiconductor manufacturing system is provided. Plural first transistors are formed and a first VtMM value and a first scale value are obtained. Plural second transistors are formed and a second VtMM value and a second scale value are obtained. Plural third transistors are formed and a third VtMM value and a third scale value are obtained. A first channel length of the first transistor is smaller than a second channel length of the second transistor and is equal to a third channel length of the third transistor. A VtMM v.s. scale figure is established. A line is formed by linking the first dot and the third dot and a vertical Gap between the line and the second dot is measured. The capability of the semiconductor system is determined based on the vertical Gap. The invention further provides a chip.

Abstract translation: 提供了一种估计半导体制造系统的能力的方法。 形成多个第一晶体管，并获得第一VtMM值和第一刻度值。 形成多个第二晶体管，并获得第二VtMM值和第二刻度值。 形成多个第三晶体管，并获得第三VtMM值和第三比例值。 第一晶体管的第一沟道长度小于第二晶体管的第二沟道长度，并且等于第三晶体管的第三沟道长度。 VtMM v.s. 规模建立。 通过连接第一点和第三点形成线，并且测量线与第二点之间的垂直间隙。 基于垂直间隙确定半导体系统的能力。 本发明还提供一种芯片。

公开(公告)号：US10177132B2

公开(公告)日：2019-01-08

申请号：US15088122

申请日：2016-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Tzu-Feng Chang ,  Wei-Chi Lee

IPC: G06F17/50 ,  H01L27/02 ,  G03F1/36 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access transistor, a second inner access transistor, a first outer access transistor and a second outer access transistor are electrically connected to the latch circuit, wherein the first outer access transistor has a first gate length, the first inner access transistor has a second gate length, and the first gate length is different from the second gate length.

公开(公告)号：US20150123130A1

公开(公告)日：2015-05-07

申请号：US14072905

申请日：2013-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mei-Chih Liao ,  Yi-Fang Tao ,  Yu-Lin Wang ,  Chung-Yuan Lee

IPC: H01L21/66 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/78 ,  H01L22/34

Abstract: A test key structure is provided. The test key structure comprises at least one semiconductor element. Each of the at least one semiconductor element including a well, a source region, a drain region and a gate. The source region is disposed in the well. The drain region is disposed in the well and separated from the source region. The gate is disposed above the well. The source region, the drain region and the well have the same type of doping.

Abstract translation: 提供测试键结构。 测试键结构包括至少一个半导体元件。 所述至少一个半导体元件中的每一个包括阱，源极区，漏极区和栅极。 源区域设置在井中。 漏极区域设置在阱中并与源极区域分离。 门设在井的上方。 源极区，漏极区和阱具有相同类型的掺杂。