公开(公告)号：US11004840B2

公开(公告)日：2021-05-11

申请号：US16200662

申请日：2018-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Yen ,  Tien-Hao Tang ,  Chun Chiang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H02H9/04

Abstract: A silicon controlled rectifier includes a substrate, an N-type well, a P-type well, a gate structure, a first N-type doped region, a second N-type doped region, a first P-type doped region, a second P-type doped region, a first STI, and a second STI. The N-type well and the P-type well are disposed in the substrate. The gate structure is disposed on the P-type well. The first N-type doped region is disposed in the N-type well at one side of the gate structure. The second N-type doped region is disposed in the P-type well at another side of the gate structure. The first P-type doped region is disposed in the N-type well. The second P-type doped region is disposed in the P-type well. The first STI is between the first N-type and first P-type doped regions. The second STI is between the second N-type and second P-type doped regions.

公开(公告)号：US20180254268A1

公开(公告)日：2018-09-06

申请号：US15445999

申请日：2017-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Yen ,  Po-Ya Lai ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/749 ,  H01L29/66

CPC classification number: H01L27/027 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/66356 ,  H01L29/749

Abstract: An ESD protection device includes a semiconductor substrate, a well, a gate structure, a first source/drain region, a second source/drain region, a first doped region, and a second doped region. The well is disposed in the semiconductor substrate. The gate structure is disposed on the well. The first source/drain region and the second source/drain region are disposed in the well and disposed at two opposite sides of the gate structure respectively. The first doped region is disposed in the first source/drain region. The second doped region is disposed in the second source/drain region. A conductivity type of the first doped region is complementary to that of the first source/drain region. A conductivity type of the second doped region is complementary to that of the second source/drain region. A conductivity type of the well is complementary to that of the first source/drain region and the second source/drain region.

公开(公告)号：US10068896B1

公开(公告)日：2018-09-04

申请号：US15445999

申请日：2017-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Yen ,  Po-Ya Lai ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/06 ,  H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/749 ,  H01L29/66

Abstract: An ESD protection device includes a semiconductor substrate, a well, a gate structure, a first source/drain region, a second source/drain region, a first doped region, and a second doped region. The well is disposed in the semiconductor substrate. The gate structure is disposed on the well. The first source/drain region and the second source/drain region are disposed in the well and disposed at two opposite sides of the gate structure respectively. The first doped region is disposed in the first source/drain region. The second doped region is disposed in the second source/drain region. A conductivity type of the first doped region is complementary to that of the first source/drain region. A conductivity type of the second doped region is complementary to that of the second source/drain region. A conductivity type of the well is complementary to that of the first source/drain region and the second source/drain region.