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    SEMICONDUCTOR MEMORY DEVICES
    1.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20240119984A1

    公开(公告)日：2024-04-11

    申请号：US18544996

    申请日：2023-12-19

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jaeho Hong ,  Hyuncheol Kim ,  Yongseok Kim ,  Ilgweon Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

    IPC分类号： G11C11/402 ,  G11C11/39 ,  H01L27/102 ,  H01L29/66 ,  H01L29/749

    CPC分类号： G11C11/4023 ,  G11C11/39 ,  H01L27/1027 ,  H01L29/66363 ,  H01L29/749

    摘要： A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

    Lateral insulated gate turn-off device with induced emitter
    2.
    发明授权
    Lateral insulated gate turn-off device with induced emitter 有权

    公开(公告)号：US11114553B2

    公开(公告)日：2021-09-07

    申请号：US16815856

    申请日：2020-03-11

    申请人： Pakal Technologies, Inc.

    发明人： Richard A. Blanchard ,  Vladimir Rodov

    IPC分类号： H01L29/745 ,  H01L29/749 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

    摘要： A lateral insulated gate turn-off device includes an n-drift layer, a p-well formed in the n− drift layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, a trenched first gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, an anode electrode electrically contacting the p+ type anode region, and a trenched second gate extending from the p+ type anode region into the n-drift layer. For turning the device on, a positive voltage is applied to the first gate the reduce the base width of the npn transistor, and a negative voltage is applied to the second gate to effectively extend the p+ emitter of the pnp transistor further into the n-drift layer to improve performance.

    Array of gated devices and methods of forming an array of gated devices
    6.
    发明授权
    Array of gated devices and methods of forming an array of gated devices 有权

    公开(公告)号：US10153194B2

    公开(公告)日：2018-12-11

    申请号：US15584413

    申请日：2017-05-02

    申请人： Micron Technology, Inc.

    发明人： Marcello D. Mariani ,  Anna Maria Conti ,  Sara Vigano

    IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L29/744 ,  H01L21/308 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/8239 ,  H01L27/102 ,  H01L21/8229 ,  H01L27/105 ,  H01L29/423 ,  H01L29/749

    摘要： An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.