公开(公告)号：US09196723B1

公开(公告)日：2015-11-24

申请号：US14564050

申请日：2014-12-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Yu Chen ,  Tseng-Hsun Liu ,  Min-Hsuan Tsai ,  Te-Chang Chiu ,  Chiu-Ling Lee ,  Chiu-Te Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/45

CPC classification number: H01L29/782 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1079 ,  H01L29/45 ,  H01L29/665 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7823 ,  H01L29/872

Abstract: The present invention provides a semiconductor device structure which integrates a lateral diffused metal oxide semiconductor (LDMOS) with a Schottky diode, including: a substrate, having a first conductivity type, a gate positioned on the substrate, a drain region formed in the substrate, the drain region having a second conductivity type complementary to the first conductivity type, a source region formed in the substrate, the source region having the second conductivity type, a high-voltage well region formed in the substrate, the high-voltage well region having a first conductivity type; a Schottky diode disposed on the substrate and disposed beside the LDMOS, wherein the semiconductor device structure is an asymmetric structure, and a deep well region disposed in the substrate and having the second conductivity type, wherein the LDMOS and the Schottky diode are all formed within the deep well region.

Abstract translation: 本发明提供了一种将横向扩散金属氧化物半导体（LDMOS）与肖特基二极管集成的半导体器件结构，包括：具有第一导电类型的衬底，位于衬底上的栅极，形成在衬底中的漏极区， 所述漏极区域具有与所述第一导电类型互补的第二导电类型，形成在所述衬底中的源极区域，具有第二导电类型的源极区域，形成在所述衬底中的高压阱区域，所述高压阱区域具有 第一导电类型; 设置在衬底上并设置在LDMOS旁边的肖特基二极管，其中半导体器件结构是不对称结构，以及设置在衬底中并且具有第二导电类型的深阱区，其中LDMOS和肖特基二极管全部形成在 深井区域。