公开(公告)号：US20190245041A1

公开(公告)日：2019-08-08

申请号：US15924001

申请日：2018-03-16

申请人： United Microelectronics Corp.

发明人： Yen-Ming Chen ,  Chiu-Ling Lee ,  Min-Hsuan Tsai ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC分类号： H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/1079 ,  H01L29/0649 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835

摘要： A transistor structure including a substrate, a transistor device, a split buried layer, and a second buried layer is provided. The substrate has a device region. The transistor device is located in the device region. The split buried layer is located under the transistor device in the substrate and includes first buried layers separated from each other. The second buried layer is located under the split buried layer in the substrate and connects the first buried layers. The second buried layer and the split buried layer have a first conductive type. The transistor structure may have a higher breakdown voltage.

公开(公告)号：US20190165158A1

公开(公告)日：2019-05-30

申请号：US15822408

申请日：2017-11-27

申请人： SANKEN ELECTRIC CO., LTD.

发明人： Shunsuke FUKUNAGA ,  Taro KONDO ,  Shinji KUDOH

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/10 ,  H01L29/36 ,  H01L29/66

CPC分类号： H01L29/7811 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor device may comprise a substrate; a trench formed in the substrate and filled with an insulating layer; and a gate electrode and a source embedded in the insulating layer. The gate electrode and the source electrode may be positioned in the insulating layer in the trench above and below each other. From a cross-sectional perspective, the gate electrode and the source electrode are not overlapped in horizontal or vertical direction. The trench may extend to a first depth of a bottom surface of the trench below the gate electrode, and may extend to a second depth of the bottom surface of the trench below the source electrode. The first depth and the second depth may be different.

公开(公告)号：US20180342506A1

公开(公告)日：2018-11-29

申请号：US16053607

申请日：2018-08-02

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Ji Pan ,  Sik Lui

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/02 ,  H02M3/158 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306

CPC分类号： H01L27/088 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/823487 ,  H01L27/0207 ,  H01L29/0696 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66621 ,  H02M3/158

摘要： A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal of the switch circuit, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off. The first MOS transistor is characterized by a first reverse gate-to-drain capacitance (Crss) and the second MOS transistor is characterized by a second Crss that is greater than the first Crss.

公开(公告)号：US20180261695A1

公开(公告)日：2018-09-13

申请号：US15976510

申请日：2018-05-10

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio MASUOKA ,  Nozomu HARADA

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L29/417 ,  H01L29/10 ,  H01L21/8238

CPC分类号： H01L29/7827 ,  H01L21/8238 ,  H01L29/0676 ,  H01L29/1079 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66712 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/78642

摘要： The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate (1a), a Si pillar (4a) and an impurity region (12a) located in a lower portion of the Si pillar (4a) and serving as a source or a drain, a step of forming a SiO2 layer that extends in a horizontal direction and is connected to an entire periphery of the impurity region (12a) in plan view, a step of forming a SiO2 layer (11a) on the SiO2 layer such that the SiO2 layer (11a) surrounds the Si pillar (4a) in plan view, a step of forming a resist layer (13) that is partly connected to the SiO2 layer (11a) in plan view, and a step of forming a SiO2 layer (8a) by etching the SiO2 layer below the SiO2 layer (11a) and the resist layer (13) using the SiO2 layer (11a) and the resist layer (13) as masks.

公开(公告)号：US20180190754A1

公开(公告)日：2018-07-05

申请号：US15593479

申请日：2017-05-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Chiun LIN ,  Po-Nien CHEN ,  Chen Hua TSAI ,  Chih-Yung LIN

IPC分类号： H01L49/02 ,  H01L29/10 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/3205 ,  H01L27/06

CPC分类号： H01L28/24 ,  H01L21/32051 ,  H01L21/823431 ,  H01L21/823493 ,  H01L21/823821 ,  H01L23/5228 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0924 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

公开(公告)号：US09972687B1

公开(公告)日：2018-05-15

申请号：US15464536

申请日：2017-03-21

申请人： Wisconsin Alumni Research Foundation

发明人： Chang-Beom Eom ,  Daesu Lee

IPC分类号： H01L29/24 ,  H01L21/36 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H03K17/51 ,  H01L45/00 ,  H01L21/02 ,  H03K17/687

CPC分类号： H01L29/24 ,  H01L21/02414 ,  H01L21/02483 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/1033 ,  H01L29/1079 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869 ,  H01L45/065 ,  H01L45/1206 ,  H01L45/146 ,  H03K17/04 ,  H03K17/51 ,  H03K17/687

摘要： Layers of high quality VO2 and methods of fabricating the layers of VO2 are provided. The layers are composed of a plurality of connected crystalline VO2 domains having the same crystal structure and the same epitaxial orientation.

公开(公告)号：US09935099B2

公开(公告)日：2018-04-03

申请号：US14956398

申请日：2015-12-02

申请人： UNITED MICROELECTRONICS CORP.

发明人： Zhibiao Zhou ,  Chen-Bin Lin ,  Su Xing ,  Chi-Chang Shuai ,  Chung-Yuan Lee

IPC分类号： H01L27/06 ,  H01L23/535 ,  H01L29/22 ,  H01L29/861 ,  H01L29/10 ,  H01L29/24 ,  H01L49/02 ,  H01L29/06

CPC分类号： H01L27/0629 ,  H01L23/535 ,  H01L27/0727 ,  H01L28/00 ,  H01L28/40 ,  H01L29/0603 ,  H01L29/1079 ,  H01L29/22 ,  H01L29/24 ,  H01L29/861

摘要： The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.

公开(公告)号：US20180040729A1

公开(公告)日：2018-02-08

申请号：US15785677

申请日：2017-10-17

申请人： Infineon Technologies Dresden GmbH

发明人： Andreas MEISER ,  Karl-Heinz GEBHARDT ,  Till SCHLOESSER ,  Detlef WEBER

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L29/10 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40

CPC分类号： H01L29/7825 ,  H01L21/223 ,  H01L21/2236 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7821 ,  H01L29/7835

摘要： A semiconductor device and a method of manufacturing the same is provided. The semiconductor device including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.

公开(公告)号：US09887285B1

公开(公告)日：2018-02-06

申请号：US15444238

申请日：2017-02-27

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Tsuyoshi Oota ,  Masaru Furukawa

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L27/07 ,  H01L29/10

CPC分类号： H01L29/7805 ,  H01L27/0727 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/7806

摘要： A semiconductor device comprises a silicon carbide layer, a first electrode, a second electrode, and a gate. The silicon carbide layer has first region of first conductivity type between the first and second electrodes and also the gate and second electrode. A second region of the first type is between the first electrode and the first region. A third region of second conductivity type is between the first electrode and the second region. A fourth region of the first type is between the first electrode and the third region. A fifth region of the first type is between the gate and the second region. The third region is between the fourth and fifth regions. A sixth region of the first type contacts the first electrode and is between the second region and this electrode. An insulation layer is between the gate and the third region and also the fifth region.

公开(公告)号：US20180006162A1

公开(公告)日：2018-01-04

申请号：US15400201

申请日：2017-01-06

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

发明人： FEI ZHOU

IPC分类号： H01L29/93 ,  H01L29/66 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/768

CPC分类号： H01L29/93 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66174 ,  H01L29/66181 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7851 ,  H01L29/94

摘要： A varactor transistor includes a semiconductor fin having a first conductivity type, a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin. The plurality of gates structures include a dummy gate structure on an edge of the semiconductor fin, and a first gate structure spaced apart from the dummy gate structure. The dummy gate structure and the gate structure each include a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate. The varactor transistor also includes a raised source/drain region on the semiconductor fin and between the dummy gate structure and the first gate structure, the raised source/drain region and the gate of the dummy gate structure being electrically connected to a same potential.