公开(公告)号：US10410684B2

公开(公告)日：2019-09-10

申请号：US15900811

申请日：2018-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ting-Hao Chang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Shih-Hao Liang ,  Chun-Hsien Huang ,  Shu-Ru Wang ,  Hsin-Chih Yu

IPC: G11C5/02 ,  H01L27/108 ,  H01L27/105 ,  G11C11/409 ,  G11C11/419 ,  H01L27/11 ,  H01L29/786

Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.

公开(公告)号：US10032777B1

公开(公告)日：2018-07-24

申请号：US15613288

申请日：2017-06-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Wen Chen ,  Chi-Chang Shuai ,  Hung-Chan Lin ,  Ting-Hao Chang ,  Hsien-Hung Tsai

IPC: H01L27/108 ,  G06F12/0846

Abstract: An array of dynamic random access memory cells includes a first set of memory cell pairs in a first row, a second set of memory cells in a second row, and a first set of bit line contacts in the first row. The second set of memory cell pairs are disposed adjacent to the first set of memory cell pairs, and each two of the memory cell pairs in the second row include a common S/D region. Each of the first set of bit line contacts is electrically coupled to each of the common S/D regions of the memory cell pairs in the second row respectively.

公开(公告)号：US20190221238A1

公开(公告)日：2019-07-18

申请号：US15900811

申请日：2018-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ting-Hao Chang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Shih-Hao Liang ,  Chun-Hsien Huang ,  Shu-Ru Wang ,  Hsin-Chih Yu

IPC: G11C5/02 ,  H01L27/108 ,  H01L27/105 ,  H01L27/11 ,  G11C11/409 ,  G11C11/419

CPC classification number: G11C5/02 ,  G11C11/409 ,  G11C11/419 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/1108 ,  H01L29/7869

Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.