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    Ternary content addressable memory and two-port static random access memory
    1.
    发明授权
    Ternary content addressable memory and two-port static random access memory 有权

    公开(公告)号：US11475952B2

    公开(公告)日：2022-10-18

    申请号：US17179418

    申请日：2021-02-19

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng ,  Chun-Chieh Chang

    IPC分类号： G11C15/04

    摘要： A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

    Two-port ternary content addressable memory and layout pattern thereof, and associated memory device
    2.
    发明授权
    Two-port ternary content addressable memory and layout pattern thereof, and associated memory device 有权

    公开(公告)号：US10892013B2

    公开(公告)日：2021-01-12

    申请号：US16439680

    申请日：2019-06-12

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng

    IPC分类号： G11C15/00 ,  G11C29/00 ,  G11C15/04 ,  H01L27/11 ,  H01L27/02 ,  G06F7/74

    摘要： A two-port ternary content addressable memory (TCAM) and layout pattern thereof, and associated memory device are provided. The two-port TCAM may include a first storage unit, a second storage unit, a set of first search terminals, a set of second search terminals, a first comparison circuit, a second comparison circuit, a first match terminal and a second match terminal, wherein the first comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of first search terminals and the first match terminal, and the second comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of second search terminals and the second match terminal. First search data and second search data may be concurrently inputted into the two-port TCAM for determining whether the first search data and the second search data match content data within the two-port TCAM.

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20180286474A1

    公开(公告)日：2018-10-04

    申请号：US15589985

    申请日：2017-05-08

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chien-Hung Chen ,  Meng-Ping Chuang ,  Tong-Yu Chen ,  Yu-Tse Kuo

    IPC分类号： G11C11/406 ,  G11C11/407

    CPC分类号： G11C5/025 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

    摘要： A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.

    Semiconductor structure
    8.
    发明授权
    Semiconductor structure 有权

    公开(公告)号：US09859282B1

    公开(公告)日：2018-01-02

    申请号：US15280333

    申请日：2016-09-29

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Shu-Ru Wang

    IPC分类号： H01L27/108 ,  H01L29/78

    CPC分类号： H01L27/10805 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

    摘要： A high-density semiconductor structure includes a substrate, a bit line and a first memory unit. The bit line, disposed on the substrate, has a first side and a second side. The first memory unit includes a first transistor, a first capacitor, a second transistor and a second capacitor. The first transistor disposed on the substrate has a first terminal and a second terminal. The first terminal connects the bit line. The first capacitor connects the second terminal of the first transistor. The second transistor disposed on the substrate has a third terminal and a fourth terminal. The third terminal connects the bit line. The second capacitor connects the fourth terminal of the second transistor. The first capacitor and the second capacitor are separated from the bit line in a direction perpendicular to an extending direction of the bit line and located on the first side of the bit line.

    Layout configuration for memory cell array
    10.
    发明授权
    Layout configuration for memory cell array 有权
    存储单元阵列的布局配置

    公开(公告)号：US09166003B2

    公开(公告)日：2015-10-20

    申请号：US14062914

    申请日：2013-10-25

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Meng-Ping Chuang ,  Yu-Tse Kuo ,  Chia-Chun Sun ,  Yun-San Huang

    IPC分类号： H01L29/06 ,  H01L27/02 ,  H01L27/11

    CPC分类号： H01L29/0692 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/0684

    摘要： A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.

    摘要翻译： 存储单元阵列的布局配置至少包括具有第一导电类型的梳状掺杂区域和具有第二导电类型的鱼骨形掺杂区域。 第二导电类型和第一导电类型是互补的。 此外，梳状掺杂区域和鱼骨形掺杂区域是交错的。