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    Layout of semiconductor memory device
    1.
    发明授权
    Layout of semiconductor memory device 有权

    公开(公告)号：US11915755B2

    公开(公告)日：2024-02-27

    申请号：US17580591

    申请日：2022-01-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Meng-Ping Chuang ,  Li-Ping Huang ,  Yu-Fang Chen

    IPC: G11C15/04

    CPC classification number: G11C15/04

    Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

    Control circuit used for ternary content-addressable memory with two logic units
    6.
    发明授权
    Control circuit used for ternary content-addressable memory with two logic units 有权

    公开(公告)号：US10366756B1

    公开(公告)日：2019-07-30

    申请号：US16104946

    申请日：2018-08-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Shu-Ru Wang

    IPC: G11C15/00 ,  G11C15/04

    Abstract: A control circuit for a ternary content-addressable memory includes a first logic unit and a second logic unit. The first logic unit is coupled to a first storage unit, a second storage unit, a first search line, a second search line, a reference voltage terminal, and a match line. The second logic unit is coupled to the first storage unit, the second storage unit, the first search line, the second search line, a first power supply line and a second power supply line. When voltages at the first search line and the second search line match voltages at the first storage unit and the second storage unit, the second logic unit provides a path for electrically connecting the first power supply line to the second power supply line.

    Ternary content addressable memory and two-port static random access memory
    7.
    发明授权
    Ternary content addressable memory and two-port static random access memory 有权

    公开(公告)号：US11475952B2

    公开(公告)日：2022-10-18

    申请号：US17179418

    申请日：2021-02-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng ,  Chun-Chieh Chang

    IPC: G11C15/04

    Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

    Two-port ternary content addressable memory and layout pattern thereof, and associated memory device
    8.
    发明授权
    Two-port ternary content addressable memory and layout pattern thereof, and associated memory device 有权

    公开(公告)号：US10892013B2

    公开(公告)日：2021-01-12

    申请号：US16439680

    申请日：2019-06-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Yen Tseng

    IPC: G11C15/00 ,  G11C29/00 ,  G11C15/04 ,  H01L27/11 ,  H01L27/02 ,  G06F7/74

    Abstract: A two-port ternary content addressable memory (TCAM) and layout pattern thereof, and associated memory device are provided. The two-port TCAM may include a first storage unit, a second storage unit, a set of first search terminals, a set of second search terminals, a first comparison circuit, a second comparison circuit, a first match terminal and a second match terminal, wherein the first comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of first search terminals and the first match terminal, and the second comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of second search terminals and the second match terminal. First search data and second search data may be concurrently inputted into the two-port TCAM for determining whether the first search data and the second search data match content data within the two-port TCAM.

    Semiconductor structure
    10.
    发明授权
    Semiconductor structure 有权

    公开(公告)号：US09859282B1

    公开(公告)日：2018-01-02

    申请号：US15280333

    申请日：2016-09-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Shu-Ru Wang

    IPC: H01L27/108 ,  H01L29/78

    CPC classification number: H01L27/10805 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

    Abstract: A high-density semiconductor structure includes a substrate, a bit line and a first memory unit. The bit line, disposed on the substrate, has a first side and a second side. The first memory unit includes a first transistor, a first capacitor, a second transistor and a second capacitor. The first transistor disposed on the substrate has a first terminal and a second terminal. The first terminal connects the bit line. The first capacitor connects the second terminal of the first transistor. The second transistor disposed on the substrate has a third terminal and a fourth terminal. The third terminal connects the bit line. The second capacitor connects the fourth terminal of the second transistor. The first capacitor and the second capacitor are separated from the bit line in a direction perpendicular to an extending direction of the bit line and located on the first side of the bit line.

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