MASK AND METHOD OF FORMING PATTERN BY USING THE SAME
    1.
    发明申请
    MASK AND METHOD OF FORMING PATTERN BY USING THE SAME 有权
    使用它形成图案的掩模和方法

    公开(公告)号:US20150128099A1

    公开(公告)日:2015-05-07

    申请号:US14591937

    申请日:2015-01-08

    Inventor: Yu-Shiang Yang

    CPC classification number: G03F1/36 G03F1/38 G06F17/5068

    Abstract: A method of forming a pattern is disclosed. At first, a layout pattern is provided to a computer system. The layout pattern includes at least a first strip pattern and at least a second strip pattern, and a width of the second strip pattern is substantially larger than a width of the first strip pattern. Subsequently, the second strip pattern neighboring the first strip pattern is defined as a selected pattern. Then, an assist pattern is formed in the selected pattern, and the assist pattern does not overlap a center line of the selected pattern. The layout pattern and the assist pattern are further outputted through the computer system onto a mask.

    Abstract translation: 公开了形成图案的方法。 首先,向计算机系统提供布局图案。 布局图案至少包括第一条带图案和至少第二条纹图案,并且第二条纹图案的宽度基本上大于第一条纹图案的宽度。 随后,与第一条带图案相邻的第二带状图案被定义为所选择的图案。 然后,在所选择的图案中形成辅助图案,并且辅助图案不与所选图案的中心线重叠。 布局图案和辅助图案通过计算机系统进一步输出到面罩上。

    METHOD FOR MANUFACTURING SEMICONDUCTOR LAYOUT PATTERN, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR LAYOUT PATTERN, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE 有权
    用于制造半导体布局图案的方法,制造半导体器件的方法和半导体器件

    公开(公告)号:US20140131832A1

    公开(公告)日:2014-05-15

    申请号:US13674965

    申请日:2012-11-13

    CPC classification number: H01L29/02 H01L21/3081 H01L21/3086 H01L21/76224

    Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a mask layer formed thereon, providing a first photomask having a first layout pattern and a second photomask having a second layout pattern, the first layout pattern including a plurality of active area portions and at least a neck portion connecting two adjacent active area portions, transferring the first layout pattern from the first photomask to the mask layer to form a plurality of active area patterns and at least a neck pattern connecting two adjacent active area patterns in the mask layer, and transferring the second layout pattern from the second photomask to the mask layer to remove the neck pattern to form a patterned mask. The patterned mask includes the active area patterns. A slot is at least formed between the two adjacent active area patterns.

    Abstract translation: 一种制造半导体器件的方法,包括提供其上形成有掩模层的衬底,提供具有第一布局图案的第一光掩模和具有第二布局图案的第二光掩模,所述第一布局图案包括多个有效区域部分, 连接两个相邻有效区域部分的至少一个颈部部分,将第一布局图案从第一光掩模转移到掩模层以形成多个有源区域图案和至少连接掩模层中的两个相邻有源区域图案的颈部图案,以及 将第二布局图案从第二光掩模转印到掩模层以去除颈部图案以形成图案化掩模。 图案化掩模包括有源区域图案。 至少在两个相邻有效区域图案之间形成槽。

    Mask and method of forming pattern by using the same
    3.
    发明授权
    Mask and method of forming pattern by using the same 有权
    通过使用其形成图案的掩模和方法

    公开(公告)号:US09268209B2

    公开(公告)日:2016-02-23

    申请号:US14591937

    申请日:2015-01-08

    Inventor: Yu-Shiang Yang

    CPC classification number: G03F1/36 G03F1/38 G06F17/5068

    Abstract: A method of forming a pattern is disclosed. At first, a layout pattern is provided to a computer system. The layout pattern includes at least a first strip pattern and at least a second strip pattern, and a width of the second strip pattern is substantially larger than a width of the first strip pattern. Subsequently, the second strip pattern neighboring the first strip pattern is defined as a selected pattern. Then, an assist pattern is formed in the selected pattern, and the assist pattern does not overlap a center line of the selected pattern. The layout pattern and the assist pattern are further outputted through the computer system onto a mask.

    Abstract translation: 公开了形成图案的方法。 首先,向计算机系统提供布局图案。 布局图案至少包括第一条带图案和至少第二条纹图案,并且第二条纹图案的宽度基本上大于第一条纹图案的宽度。 随后,与第一条带图案相邻的第二带状图案被定义为所选择的图案。 然后,在所选择的图案中形成辅助图案,并且辅助图案不与所选图案的中心线重叠。 布局图案和辅助图案通过计算机系统进一步输出到面罩上。

    Method for manufacturing semiconductor layout pattern, method for manufacturing semiconductor device, and semiconductor device
    4.
    发明授权
    Method for manufacturing semiconductor layout pattern, method for manufacturing semiconductor device, and semiconductor device 有权
    半导体布局图案的制造方法,半导体装置的制造方法以及半导体装置

    公开(公告)号:US09171898B2

    公开(公告)日:2015-10-27

    申请号:US13674965

    申请日:2012-11-13

    CPC classification number: H01L29/02 H01L21/3081 H01L21/3086 H01L21/76224

    Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a mask layer formed thereon, providing a first photomask having a first layout pattern and a second photomask having a second layout pattern, the first layout pattern including a plurality of active area portions and at least a neck portion connecting two adjacent active area portions, transferring the first layout pattern from the first photomask to the mask layer to form a plurality of active area patterns and at least a neck pattern connecting two adjacent active area patterns in the mask layer, and transferring the second layout pattern from the second photomask to the mask layer to remove the neck pattern to form a patterned mask. The patterned mask includes the active area patterns. A slot is at least formed between the two adjacent active area patterns.

    Abstract translation: 一种制造半导体器件的方法,包括提供其上形成有掩模层的衬底,提供具有第一布局图案的第一光掩模和具有第二布局图案的第二光掩模,所述第一布局图案包括多个有效区域部分, 连接两个相邻有效区域部分的至少一个颈部部分,将第一布局图案从第一光掩模转移到掩模层以形成多个有源区域图案和至少连接掩模层中的两个相邻有源区域图案的颈部图案,以及 将第二布局图案从第二光掩模转印到掩模层以去除颈部图案以形成图案化掩模。 图案化掩模包括有源区域图案。 至少在两个相邻有效区域图案之间形成槽。

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