公开(公告)号：US20240355633A1

公开(公告)日：2024-10-24

申请号：US18762702

申请日：2024-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yen Chen

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/3086 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

Abstract: A method includes forming an etching mask to cover a mandrel, a first spacer, and a second spacer, and the first spacer and the second spacer are in contact with opposing sidewalls of the mandrel. The etching mask is then patterned, and includes a first portion covering the first spacer, a second portion covering the second spacer, and a bridge portion connecting the first portion to the second portion. The bridge portion has first sidewalls. A first etching process is performed on the mandrel using the etching mask to define pattern, and after the first etching process, the mandrel includes a second bridge portion having second sidewalls vertically aligned to corresponding ones of the first sidewalls. After the mandrel is etched-through, a second etching process is performed to laterally recess the second bridge portion of the mandrel.

公开(公告)号：US20240355632A1

公开(公告)日：2024-10-24

申请号：US18638335

申请日：2024-04-17

Applicant: SHIN-ETSU CHEMICAL CO., LTD.

Inventor： Yasuyuki YAMAMOTO ,  Tomohiro IMATA ,  Daisuke KORI

IPC: H01L21/308 ,  G03F7/09 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/3081 ,  G03F7/094 ,  H01L21/0275 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: The present invention is a composition for forming an organic film, comprising: a resin for forming an organic film; a polymer having a unit represented by the general formula (I), and at least one of a unit represented by the general formula (II) and a unit represented by the general formula (III); and a solvent, wherein the unit represented by the general formula (I), and at least one of the unit represented by the general formula (II) and the unit represented by the general formula (III) form a random copolymer, and the polymer has a fluorine content of 5 mass % to 16 mass %. This provides: a composition for forming an organic film that has excellent film-formability on a substrate and filling characteristics, and that inhibits humps in EBR process; and a method for forming an organic film, and patterning process using this composition.

公开(公告)号：US12125852B2

公开(公告)日：2024-10-22

申请号：US18360895

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/027 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L27/0886 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/3086

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US20240332059A1

公开(公告)日：2024-10-03

申请号：US18390026

申请日：2023-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngin KIM ,  BYOUNGHO KWON ,  Yeil KIM ,  JONGHYUK PARK ,  JIN-WOO BAE ,  KYOUNGJOON SONG ,  MYUNGJAE JANG ,  Byungsoo JOO

IPC: H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L21/762 ,  H01L21/30625 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76831 ,  H01L21/76832

Abstract: A method of fabricating a semiconductor device includes forming, in a semiconductor substrate, a device isolation trench defining active regions, forming a first liner dielectric layer covering a top surface of the semiconductor substrate and an inner wall of the device isolation trench, forming a second liner dielectric layer covering the first liner dielectric layer, forming a buried dielectric layer filling the device isolation trench, performing a polishing process on the second liner dielectric layer and the buried dielectric layer to form a device isolation structure, forming a mask pattern running across the active regions, and partially patterning the active regions and the device isolation structure to form gate trenches. After the polishing process, the first liner dielectric layer, the second liner dielectric layer, and the buried dielectric layer have their top surfaces formed by the polishing process coplanar with each other.

公开(公告)号：US12100597B2

公开(公告)日：2024-09-24

申请号：US17712017

申请日：2022-04-01

Applicant: ASM IP Holding B.V.

Inventor： Eiichiro Shiba

IPC: H01L21/308 ,  C23C16/34 ,  C23C16/455 ,  C23C16/515 ,  C23C16/56 ,  H01J37/32 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/3086 ,  C23C16/345 ,  C23C16/45538 ,  C23C16/45544 ,  C23C16/515 ,  C23C16/56 ,  H01J37/32449 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31122 ,  H01J2237/332 ,  H01J2237/334 ,  H01L21/3081

Abstract: Methods of forming patterned structures suitable for a multiple patterning process are disclosed. Exemplary methods include forming a silicon nitride layer overlying the substrate by providing a silicon precursor to the reaction chamber for a silicon precursor pulse period, providing a nitrogen reactant to the reaction chamber, providing a hydrogen reactant to the reaction chamber, and providing a plasma power to form a plasma within the reaction chamber for a plasma pulse period. An etch profile of sacrificial features on the substrate can be controlled by controlling an amount of hydrogen provided to the reaction chamber and/or using other process parameters.

公开(公告)号：US12099299B2

公开(公告)日：2024-09-24

申请号：US18354388

申请日：2023-07-18

Applicant: Tokyo Electron Limited

Inventor： Jodi Grzeskowiak ,  Anthony Schepis ,  Anton Devilliers

IPC: G03F7/09 ,  G03F7/004 ,  G03F7/11 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308

CPC classification number: G03F7/094 ,  G03F7/0045 ,  G03F7/091 ,  G03F7/11 ,  H01L21/0276 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088

Abstract: A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.

公开(公告)号：US20240315018A1

公开(公告)日：2024-09-19

申请号：US18676056

申请日：2024-05-28

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H10B41/35 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/67 ,  H01L21/768 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/35 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/67063 ,  H01L21/76802 ,  H10B20/383 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H01L2221/1063 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240304446A1

公开(公告)日：2024-09-12

申请号：US18574802

申请日：2022-06-20

Applicant: JENOPTIK Optical Systems GmbH

Inventor： Meik PANITZ ,  Lutz RAUPACH ,  Martin TILKE ,  Sabine ZYBELL

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/0337 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086

Abstract: A method of producing an etching mask. A substrate is provided, a metal layer is applied, the metal layer comprises or is formed from at least one transition metal and/or aluminum. A masking layer is applied and the masking layer is structured. The metal layer is exposed in at least one processing region. The substrate is coated with a tetrel layer including at least partially a tetrel, wherein an interdiffusion zone between the transition metal or aluminum and the tetrel is formed in the processing region at an interface between the metal layer and the tetrel layer. The masking layer is removed and the metal layer s selectively etched. The substrate is exposed in at least one etching region other than the processing region, and the metal layer is at least partially maintained in the processing region.

公开(公告)号：US20240302747A1

公开(公告)日：2024-09-12

申请号：US18281993

申请日：2022-03-15

Applicant: NISSAN CHEMICAL CORPORATION

Inventor： Hiroto OGATA ,  Ryuta MIZUOCHI ,  Tomotada HIROHARA ,  Mamoru TAMURA

IPC: G03F7/11 ,  G03F7/16 ,  G03F7/20 ,  H01L21/027 ,  H01L21/308

CPC classification number: G03F7/11 ,  G03F7/168 ,  G03F7/2004 ,  H01L21/0275 ,  H01L21/3081 ,  H01L21/3086

Abstract: A composition for forming a resist underlayer film that enables the formation of a desired resist pattern; a method for producing a resist pattern, the method using this resist underlayer film-forming composition; and a method for producing a semiconductor device. The resist underlayer film-forming composition includes a solvent and a product of reaction between compound (A) represented by formula (100) below. In formula (100), Ar1 and Ar2 each independently represent a C6-C40 aromatic ring that may be substituted, at least one of Ar1 and Ar2 is a naphthalene ring, L1 represents a single bond, a C1-C10 alkylene group that may be substituted, or a C2-C10 alkenylene group that may be substituted, T1 and T2 each independently represent a single bond, an ester bond or an ether bond, and E represents an epoxy group) and compound (B) containing at least two groups having reactivity with an epoxy group.

公开(公告)号：US20240297048A1

公开(公告)日：2024-09-05

申请号：US18657487

申请日：2024-05-07

Applicant: GE Precision Healthcare LLC

Inventor： Shubhodeep Goswami ,  David Milford Shaddock ,  Matthew David Butts ,  Gregory Keith Dudoff

IPC: H01L21/308 ,  B81C1/00 ,  G21K1/06 ,  H01L21/3065

CPC classification number: H01L21/3086 ,  B81C1/00555 ,  G21K1/067 ,  H01L21/3065

Abstract: The present techniques relate to various aspects of forming and filling high-aspect ratio trench structures (e.g., trench structures having an aspect ratio of 20 or greater, including aspect ratios in the range of 20:1 up to and including 50:1 or greater) combined with trench opening widths ranging from 0.5 micron to 50 microns. By way of example, patterned substrate described herein includes a substrate, a mask layer deposited on the substrate, and a photoresist layer deposited on the mask layer. The photoresist layer is patterned to form a pattern and the mask layer is etched through the pattern to expose the substrate. The substrate is etched through the pattern to form a structure comprising a plurality of trenches having vertical sidewall. The photoresist layer remains on the mask layer during etching of the substrate.