公开(公告)号：US20240047225A1

公开(公告)日：2024-02-08

申请号：US17903417

申请日：2022-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Ju WEI ,  Chung-Yi CHIU ,  Zhen WU ,  Hsuan-Hsu CHEN ,  Chun-Lung CHEN

IPC: H01L21/3213 ,  H01J37/32

CPC classification number: H01L21/32139 ,  H01J37/32926 ,  H01J2237/334

Abstract: A control method of a multi-stage etching process and a processing device using the same are provided. The control method of the multi-stage etching process includes the following step S. A stack information of a plurality of hard mask layers is set. An etching target condition is set. Through a machine learning model, a parameter setting recipe of the hard mask layers is generated under the etching target condition. The machine learning model is trained based on the stack information of the hard mask layers, a plurality of process parameters and a process result.

公开(公告)号：US20230007939A1

公开(公告)日：2023-01-12

申请号：US17391075

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chuan-Chang WU ,  Zhen WU ,  Hsuan-Hsu CHEN ,  Chun-Lung CHEN

IPC: H01L21/3213 ,  H01L29/66

Abstract: A method for a clean procedure during manufacturing a semiconductor device, includes: providing a patterned sacrificial gate structure including a gate dielectric and a sacrificial layer; wherein the patterned sacrificial gate structure is embedded in a dielectric layer and an upper surface of the sacrificial layer is exposed; performing a first etching process to remove the sacrificial layer; and performing a hydrophilic treatment and a hydrophobic treatment to remove a residue of the sacrificial layer.