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1.发明公开公开(公告)号：US20230238262A1
公开(公告)日：2023-07-27
申请号：US17695299
申请日：2022-03-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hsiao-Ying YANG , Ching-Pei LIN , Chung-Yi CHIU , Ming-Wei CHEN , Te-Hsuan CHEN , Chia-Wei CHEN , Wen-Shan HUANG
CPC classification number: H01L21/67276 , G06N20/00
Abstract: A semiconductor manufacturing process prediction method and a semiconductor manufacturing process prediction device are provided. The semiconductor manufacturing process prediction method includes the following steps. A plurality of process data are obtained. According to the process data, a machine learning model is used to execute prediction and obtain a prediction confidence and a prediction yield. Whether the prediction confidence is lower than a predetermined level is determined. If the prediction confidence is lower than the predetermined level, the machine learning model is modified. According to the process data, the prediction yield is adjusted.
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公开(公告)号：US20230006041A1
公开(公告)日：2023-01-05
申请号：US17385961
申请日：2021-07-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jing-Wen HUANG , Wei-Hao HUANG , Chung-Yi CHIU , Lung-En KUO , Kun-Yuan LIAO
IPC: H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66
Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a plurality of nanowires. The substrate has an upper surface. The nanowires are stacked on the upper surface of the substrate along a first direction. The nanowires include a triangle in a cross section, and the nanowires include a plane extending along a second direction, a first down-slant facet on a (111) plane, and a second down-slant facet on an additional (111) plane.
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Patent Agency Ranking
公开(公告)号：US20240047225A1
公开(公告)日：2024-02-08
申请号：US17903417
申请日：2022-09-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Liang Ju WEI , Chung-Yi CHIU , Zhen WU , Hsuan-Hsu CHEN , Chun-Lung CHEN
IPC: H01L21/3213 , H01J37/32
CPC classification number: H01L21/32139 , H01J37/32926 , H01J2237/334
Abstract: A control method of a multi-stage etching process and a processing device using the same are provided. The control method of the multi-stage etching process includes the following step S. A stack information of a plurality of hard mask layers is set. An etching target condition is set. Through a machine learning model, a parameter setting recipe of the hard mask layers is generated under the etching target condition. The machine learning model is trained based on the stack information of the hard mask layers, a plurality of process parameters and a process result.
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公开(公告)号：US20230384689A1
公开(公告)日：2023-11-30
申请号：US17880700
申请日：2022-08-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shu-Yen LIU , Hui-Fang KUO , Chian-Ting HUANG , Wei-Cyuan LO , Yung-Feng CHENG , Chung-Yi CHIU
IPC: G03F7/20
CPC classification number: G03F7/70441
Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.
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公开(公告)号：US20230236553A1
公开(公告)日：2023-07-27
申请号：US17695255
申请日：2022-03-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Wei CHEN , Ching-Pei LIN , Chung-Yi CHIU , Te-Hsuan CHEN , Ming-Wei CHEN , Hsiao-Ying YANG
CPC classification number: G05B13/048 , H01L22/14 , H01L22/12
Abstract: A training method of a semiconductor process prediction model, a semiconductor process prediction device, and a semiconductor process prediction method are provided. The training method of the semiconductor process prediction model includes the following steps. The semiconductor process was performed on several samples. A plurality of process data of the samples are obtained. A plurality of electrical measurement data of the samples are obtained. Some of the samples having physical defects are filtered out according to the process data. The semiconductor process prediction model is trained according to the process data and the electrical measurement data of the filtered samples.
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公开(公告)号：US20220373877A1
公开(公告)日：2022-11-24
申请号：US17359687
申请日：2021-06-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Min-Cheng YANG , Chung-Yi CHIU
Abstract: A mask correction method, a mask correction device for double patterning, and a training method for a layout machine learning model are provided. The mask correction method for double patterning includes the following steps. A target layout is obtained. The target layout is decomposed into two sub-layouts, which overlap at a stitch region. A size of the stitch region is analyzed by the layout machine learning model according to the target layout. The layout machine learning model is established according to a three-dimensional information after etching. An optical proximity correction (OPC) procedure is performed on the sub-layouts.
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公开(公告)号：US20220365444A1
公开(公告)日：2022-11-17
申请号：US17348806
申请日：2021-06-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Guo-Xin HU , Yuh-Kwei CHAO , Chung-Yi CHIU
Abstract: An optical proximity correction (OPC) operation method and an OPC operation device are provided. The OPC operation method includes the following steps. A mask layout is obtained. If the mask layout contains at least one defect hotspot, at least one partial area pattern is extracted from the mask layout according to the at least defect hotspot. A machine learning model is used to analyze the local area pattern to obtain at least one OPC strategy. The OPC strategy is implemented to correct the mask layout.
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