公开(公告)号：US11641713B2

公开(公告)日：2023-05-02

申请号：US17483824

申请日：2021-09-24

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hung Kuo ,  Kuo-Ching Chen

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09 ,  H05K3/00

Abstract: A circuit board structure, including a circuit layer, a first dielectric layer, a first graphene layer, a first conductive via, and a first built-up circuit layer, is provided. The circuit layer includes multiple pads. The first dielectric layer is disposed on the circuit layer and has a first opening. The first opening exposes the pads. The first graphene layer is conformally disposed on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region. The first conductive via is disposed in the first opening. The first built-up circuit layer is disposed corresponding to the first conductive seed layer region. The first built-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the pads through the first conductive via and the first conductive seed layer region.

公开(公告)号：US20220285255A1

公开(公告)日：2022-09-08

申请号：US17232109

申请日：2021-04-15

Applicant: Unimicron Technology Corp.

Inventor： Yan-Jia Peng ,  Kuo-Ching Chen ,  Pu-Ju Lin

IPC: H01L23/498 ,  H05K3/46 ,  H01L23/12 ,  H01L23/528 ,  H01L23/532 ,  H01L23/16 ,  H01L23/00 ,  H01L21/50 ,  H01L21/768

Abstract: A method of fabricating a wiring board with an embedded interposer substrate includes preparing a main substrate, forming a recess on the main substrate, placing an interposer substrate into the recess, electrically connecting a second pad of the interposer substrate and the first pad of the main substrate, and filling a gap between the interposer substrate and the main substrate with an underfill. The recess exposes a first pad of the main substrate. A second pad of interposer substrate and the first pad of the main substrate are made of the same metal and formed in different outer surface profiles. The underfill entirely touches side surfaces and a bottom surface of the interposer substrate.

公开(公告)号：US11488900B2

公开(公告)日：2022-11-01

申请号：US17232109

申请日：2021-04-15

Applicant: Unimicron Technology Corp.

Inventor： Yan-Jia Peng ,  Kuo-Ching Chen ,  Pu-Ju Lin

IPC: H01L23/498 ,  H05K3/46 ,  H01L23/12 ,  H01L23/528 ,  H01L21/768 ,  H01L23/16 ,  H01L23/00 ,  H01L21/50 ,  H01L23/532

Abstract: A method of fabricating a wiring board with an embedded interposer substrate includes preparing a main substrate, forming a recess on the main substrate, placing an interposer substrate into the recess, electrically connecting a second pad of the interposer substrate and the first pad of the main substrate, and filling a gap between the interposer substrate and the main substrate with an underfill. The recess exposes a first pad of the main substrate. A second pad of interposer substrate and the first pad of the main substrate are made of the same metal and formed in different outer surface profiles. The underfill entirely touches side surfaces and a bottom surface of the interposer substrate.

公开(公告)号：US20220322529A1

公开(公告)日：2022-10-06

申请号：US17483824

申请日：2021-09-24

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hung Kuo ,  Kuo-Ching Chen

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H05K1/09

Abstract: A circuit board structure, including a circuit layer, a first dielectric layer, a first graphene layer, a first conductive via, and a first built-up circuit layer, is provided. The circuit layer includes multiple pads. The first dielectric layer is disposed on the circuit layer and has a first opening. The first opening exposes the pads. The first graphene layer is conformally disposed on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region. The first conductive via is disposed in the first opening. The first built-up circuit layer is disposed corresponding to the first conductive seed layer region. The first built-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the pads through the first conductive via and the first conductive seed layer region.