公开(公告)号：US12185479B2

公开(公告)日：2024-12-31

申请号：US17945106

申请日：2022-09-15

Applicant: Unimicron Technology Corp.

Inventor： Cheng-Ta Ko ,  Pu-Ju Lin ,  Shih-Chieh Chen ,  Chi-Hai Kuo ,  Jeng-Ting Li

IPC: H05K1/03 ,  H05K1/11 ,  H05K3/06 ,  H05K3/46

Abstract: A flexible circuit board and a manufacturing method thereof are provided. The flexible circuit board includes a circuit structure, a first cover layer, and a second cover layer. The circuit structure has a top surface and a bottom surface opposite to the top surface. The circuit structure includes multiple circuit layers and multiple insulating layers stacked alternately. A material of the insulating layers is a photosensitive dielectric material and a Young's modulus of the insulating layers is between 0.36 GPa and 8 GPa. The first cover layer is disposed on the top surface of the circuit structure. The second cover layer is disposed on the bottom surface of the circuit structure.

公开(公告)号：US12184005B2

公开(公告)日：2024-12-31

申请号：US17661282

申请日：2022-04-28

Applicant: Unimicron Technology Corp.

Inventor： Ching-Ho Hsieh ,  Ming-Hsing Wu ,  Keui-Sheng Wu

IPC: H01R13/17 ,  H01R12/70

Abstract: A connector includes a substrate, a coverlay and a spring contact. The substrate has a first surface, a second surface opposite to the first surface and a conductive through hole extending between the first and second surfaces. The coverlay is disposed on the first surface and includes a first opening. The spring contact includes an anchor member, a rising member and a pin. The anchor member is disposed between the substrate and the coverlay. The rising member extends from the anchor member and through the first opening in a direction away from the substrate. A first portion of the rising member is in the first opening, and a second portion of the rising member is out of the first opening. The pin extends from the anchor member to an inside of the conductive through hole, and is electrically connected to the conductive through hole.

公开(公告)号：US20240389232A1

公开(公告)日：2024-11-21

申请号：US18220548

申请日：2023-07-11

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Chun Hung KUO ,  Kuo-Ching CHEN ,  Yu-Cheng HUANG ,  Yu-Hua CHEN

IPC: H05K1/14 ,  H05K1/16 ,  H05K3/36

Abstract: A circuit board structure and a manufacturing method thereof. Circuit board structure includes first circuit board, second circuit board, conductive coil, magnetic body and molding compound. First circuit board has first side surface and first cavity located on first side surface. Second circuit board has second side surface facing first side surface and being spaced apart from first side surface. Conductive coil is in a spiral shape and includes first coil pattern and second coil pattern. First coil pattern is disposed in first circuit board. Second coil pattern is disposed in second circuit board. First coil pattern is electrically connected to second coil pattern. Magnetic body is filled in first cavity of first circuit board. Conductive coil surrounds at least a part of magnetic body. Molding compound is filled in a gap between first side surface and second side surface.

公开(公告)号：US12108530B2

公开(公告)日：2024-10-01

申请号：US17899583

申请日：2022-08-30

Applicant: Unimicron Technology Corp.

Inventor： Kuang-Ching Fan ,  Chih-Peng Hsieh ,  Cheng-Hsiung Wang

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/112 ,  H05K3/4644 ,  H05K1/0284 ,  H05K1/0298 ,  H05K1/113 ,  H05K2201/098

Abstract: A circuit board structure includes a circuit substrate, a first circuit layer, and a second circuit layer. The circuit substrate has a surface and includes at least one conductive structure and at least one patterned circuit layer. The conductive structure is electrically connected to the patterned circuit layer, and an upper surface of the conductive structure is aligned with the surface. The first circuit layer is directly disposed on the surface of the circuit substrate and electrically connected to the conductive structure. A line width of the first circuit layer is less than or equal to 1/4 of a line width of the patterned circuit layer. The second circuit layer is directly disposed on the first circuit layer and electrically connected to the first circuit layer.

公开(公告)号：US20240314932A1

公开(公告)日：2024-09-19

申请号：US18136358

申请日：2023-04-19

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Chen-An TSAI

IPC: H05K1/16 ,  H01F17/00 ,  H01F41/04 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/165 ,  H01F17/0013 ,  H01F41/041 ,  H05K1/115 ,  H05K3/4644 ,  H05K2201/086 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/1003

Abstract: The present invention includes an aluminum board, an electromagnet core, and a coil. The aluminum board includes a first surface, a second surface opposite to the first surface, and multiple through vias in communication with the first surface and the second surface. The electromagnet core is mounted on the first surface, and the through vias are located on two opposite sides of the electromagnet core. The coil is mounted through the through vias to wrap around the electromagnet core. An inside wall of each of the through vias forms an anodic aluminum oxide (AAO) by an anodizing process. The present invention is able to decrease via size of a conductive through via of a vertically embedded inductor. This allows through vias to be more densely formed on a board, and thus increases an amount of the coil wrapped around the electromagnetic core and increases inductance of the inductor.

公开(公告)号：US20240310428A1

公开(公告)日：2024-09-19

申请号：US18315474

申请日：2023-05-10

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hsien CHIEN ,  Hsin-Hung LEE ,  Hsuan-Yu LAI ,  Yu-Chung HSIEH

IPC: G01R31/28

CPC classification number: G01R31/2805 ,  G01R31/2808

Abstract: An inspection system and an inspection method of a bare circuit board are provided. The inspection system is used for inspecting a bare circuit board. The bare circuit board includes a chip pad and an antenna. The inspection system includes an adapter board, a test device and a measure device. The adapter board includes a chip and a contact structure. The chip is electrically connected to the contact structure. The contact structure touches the chip pad so that the chip is electrically connected to the chip pad. The test device includes a transceiver antenna. The test device and the bare circuit board separate. The measure device is electrically connected to the chip or the transceiver antenna.

公开(公告)号：US20240167163A1

公开(公告)日：2024-05-23

申请号：US18088204

申请日：2022-12-23

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： YI LING CHEN ,  WEI TSE HO ,  CHIN-SHENG WANG ,  PU-JU LIN ,  CHENG-TA KO

IPC: C23C18/42 ,  C23C18/16 ,  C23C18/32 ,  H01L21/768 ,  H01L23/48

CPC classification number: C23C18/42 ,  C23C18/1637 ,  C23C18/165 ,  C23C18/1689 ,  C23C18/32 ,  H01L21/76898 ,  H01L23/481

Abstract: An anti-diffusion substrate structure includes a substrate, a substrate circuit layer, and a chip. The substrate has multiple through holes. Within each of the through holes includes a first metal layer and an anti-diffusion layer plated on the first metal layer. The anti-diffusion layer is an Electroless Palladium Immersion Gold (EPIG) layer or an Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layer. The substrate circuit layer is mounted on the substrate and extended on the anti-diffusion layer within each of the through holes. The substrate circuit layer is made of a second metal layer, and a composition of the second metal layer is different from a composition of the first metal layer. The chip is electrically connected to the substrate circuit layer. The anti-diffusion layer is able to better prevent material of the first metal layer from migrating or diffusing to the second metal layer.

公开(公告)号：US20240128179A1

公开(公告)日：2024-04-18

申请号：US18053748

申请日：2022-11-08

Applicant: Unimicron Technology Corp.

Inventor： Jyun-Hong CHEN ,  Chi-Hai KUO ,  Pu-Ju LIN ,  Cheng-Ta KO

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/373 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/145 ,  H01L23/3737 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/1011 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/3511

Abstract: A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.

公开(公告)号：US20240121896A1

公开(公告)日：2024-04-11

申请号：US18065606

申请日：2022-12-13

Applicant: Unimicron Technology Corp.

Inventor： Chien Jung CHEN ,  Jia Hao LIANG ,  Ching Ku LIN

IPC: H05K1/11 ,  H05K3/06 ,  H05K3/46

CPC classification number: H05K1/112 ,  H05K3/062 ,  H05K3/4644

Abstract: The present disclosure provides a circuit board including a first circuit layer, a dielectric layer on the first circuit layer, and a seed layer on the dielectric layer and directly contacting the first circuit layer, in which a top surface of the seed layer includes a levelled portion. The circuit board also includes a second circuit layer on the levelled portion of the seed layer, in which a grain boundary density of the second circuit layer is lower than that of a portion of the seed layer directly contacting the first circuit layer.

公开(公告)号：US20230402391A1

公开(公告)日：2023-12-14

申请号：US17814527

申请日：2022-07-24

Applicant: Unimicron Technology Corp.

Inventor： Ying-Chu CHEN ,  Jeng-Ting LI ,  Chi-Hai KUO ,  Cheng-Ta KO ,  Pu-Ju LIN

IPC: H01L23/538 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5385 ,  H01L23/5383 ,  H01L23/293 ,  H01L21/4857 ,  H01L21/56

Abstract: A manufacturing method of a package structure includes: forming a redistribution layer on a top surface of a glass substrate; forming a protective layer on the top surface of the glass substrate; cutting the glass substrate and the protective layer such that the glass substrate has a cutting edge, in which a crack is formed in the cutting edge of the glass substrate; and heating the protective layer such that a portion of the protective layer flows towards a bottom surface of the glass substrate to cover the cutting edge of the glass substrate and fill the crack in the cutting edge of the glass substrate.