公开(公告)号：US07159069B2

公开(公告)日：2007-01-02

申请号：US10875652

申请日：2004-06-23

申请人： Vijaya P. Adusumilli ,  Nicola Telecco ,  Abbas S. Tehrani

发明人： Vijaya P. Adusumilli ,  Nicola Telecco ,  Abbas S. Tehrani

IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C7/10

CPC分类号： G11C16/26 ,  G06F11/1068 ,  G06F12/0804 ,  G06F12/0859 ,  G06F2212/2022 ,  G11C16/102

摘要： A system and method for performing a simultaneous external read operation during internal programming of a memory device is described. The memory device is configured to store data randomly and includes a source location, a destination location, a data register, and a cache register. The data register is configured to simultaneously write data to the destination and to the cache register. The system further includes a processing device (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device is additionally configured to provide for error correction if the received data is inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location.

摘要翻译： 描述用于在存储器件的内部编程期间执行同时外部读取操作的系统和方法。 存储器设备被配置为随机存储数据，并且包括源位置，目的地位置，数据寄存器和高速缓存寄存器。 数据寄存器被配置为同时将数据写入目的地和高速缓存寄存器。 该系统还包括处理装置（例如微处理器或微控制器），用于验证通过与存储装置的电气通信接收的任何数据的准确性。 如果接收到的数据不准确，则处理设备另外被配置为提供纠错，如果需要，则向数据添加随机数据，然后将纠错和/或随机的数据修改数据传送回目的地位置。