公开(公告)号：US20190251028A1

公开(公告)日：2019-08-15

申请号：US16387413

申请日：2019-04-17

申请人： Western Digital Technologies, Inc.

发明人： Kai-Lung CHENG ,  Yun-Tzuo LAI ,  Eugene LISITSYN ,  Jerry LO ,  Subhash Balakrishna PILLAI

IPC分类号： G06F12/0804 ,  G06F12/02 ,  G06F11/14 ,  G06F12/0868 ,  G06F1/30

CPC分类号： G06F12/0804 ,  G06F1/30 ,  G06F11/1471 ,  G06F12/0246 ,  G06F12/0868 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2212/1032 ,  G06F2212/2022 ,  G06F2212/7202

摘要： Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.

公开(公告)号：US20190220399A1

公开(公告)日：2019-07-18

申请号：US16245749

申请日：2019-01-11

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Ely K. Tsern

IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1009

CPC分类号： G06F12/0253 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/60 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7211

摘要： A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

公开(公告)号：US20190205038A1

公开(公告)日：2019-07-04

申请号：US16052234

申请日：2018-08-01

申请人： SK hynix Inc.

发明人： Joo Young LEE

IPC分类号： G06F3/06 ,  G06F12/0891

CPC分类号： G06F3/0613 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0891 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/7202

摘要： A data storage apparatus includes a nonvolatile memory device including a plurality of dies configured as a plurality of super blocks and a plurality of flush buffer blocks, an open super block manager configured to manage an index of an allocated open super block and a location into which data is to be written in the allocated open super block, an open flush buffer block manager configured to manage indexes of allocated open flush buffer blocks and locations into which data is to be written in the allocated open flush buffer blocks, and a processor configured to identify a first die in which a normal write operation is being performed and a second die next to the first die using the open super block manager, and select open flush buffer block included in dies other than the first die and the second die using the open flush buffer block manager.

公开(公告)号：US20180374548A1

公开(公告)日：2018-12-27

申请号：US15633479

申请日：2017-06-26

申请人： WESTERN DIGITAL TECHNOLOGIES, INC.

发明人： Stella Achtenberg ,  Eran Sharon ,  Judah Gamliel Hahn ,  Omer Fainzilber

IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G06F12/02

CPC分类号： G11C16/3418 ,  G06F11/1072 ,  G06F12/0246 ,  G06F2212/2022 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3427 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2211/562

摘要： A non-volatile storage apparatus includes a set of non-volatile memory cells, one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to encode data with a code rate prior to storage in the set of non-volatile memory cells, the code rate selected from two or more code rates according to one or more predictive indicators received with the data, the one or more predictive indicators relating to expected conditions for storage of the data in the set of non-volatile memory cells

公开(公告)号：US20180373643A1

公开(公告)日：2018-12-27

申请号：US15869867

申请日：2018-01-12

申请人： Silicon Motion, Inc.

发明人： Chien-Chung CHUNG ,  Kuan-Hui LI ,  Yi-Chang HUANG

IPC分类号： G06F12/1009

CPC分类号： G06F12/1009 ,  G06F12/0246 ,  G06F2212/1041 ,  G06F2212/2022 ,  G06F2212/657 ,  G06F2212/7201 ,  G06F2212/7206

摘要： A data storage device includes a flash memory and a flash memory controller. The flash memory controller operates the flash memory to store data, and stores a mapping table to record the mapping information between a plurality of logical addresses and a plurality of physical addresses of the flash memory. The mapping table is divided into a plurality of groups. Some of the groups are categorized into a first type of trim group and some of the logical addresses of each of the groups of the first type of trim group are included in a trim command. The flash memory controller performs the trim on the groups of the first type of trim group.

公开(公告)号：US20180351582A1

公开(公告)日：2018-12-06

申请号：US15610744

申请日：2017-06-01

申请人： Seagate Technology, LLC

发明人： Timothy Canepa

IPC分类号： H03M13/35 ,  H03M13/00 ,  G06F3/06 ,  G06F12/02 ,  H03M13/11 ,  H03M13/29 ,  G06F11/10 ,  G11C29/52

CPC分类号： H03M13/353 ,  G06F3/0608 ,  G06F3/0652 ,  G06F3/0688 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/2022 ,  G06F2212/7205 ,  G11C29/52 ,  H03M13/1105 ,  H03M13/2906 ,  H03M13/6577

摘要： Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a solid-state non-volatile memory (NVM) has a total user data storage capacity and an overprovisioning (OP) level. A control circuit writes parity data sets to the NVM each having a plurality of code words and an outer code. The code words include inner codes at an inner code rate to detect and correct read errors in a user data payload. The outer code includes parity data at an outer code rate to detect and correct read errors in the code words. A code adjustment circuit increases the inner code rate to compensate for a measured parameter associated with the NVM, and decreases the outer code rate to maintain the data capacity and OP levels above selected thresholds.

公开(公告)号：US20180329827A1

公开(公告)日：2018-11-15

申请号：US15954307

申请日：2018-04-16

申请人： Silicon Motion, Inc.

发明人： Jieh-Hsin Chien ,  Yi-Hua Pao

IPC分类号： G06F12/1009

CPC分类号： G06F12/1009 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/2022 ,  G06F2212/657 ,  G06F2212/7201

摘要： A storage device includes a flash memory array and a controller. The flash memory array stores a plurality of user data. After the controller finishes initialization, the controller accesses the user data stored in the flash memory array according to a plurality of host commands and an H2F mapping table, and records a plurality of address information about the user data in a powered-ON access table.

公开(公告)号：US20180329818A1

公开(公告)日：2018-11-15

申请号：US15593206

申请日：2017-05-11

申请人： Western Digital Technologies, Inc.

发明人： Kai-Lung CHENG ,  Yun-Tzuo LAI ,  Eugene LISITSYN ,  Jerry LO ,  Subhash Balakrishna PILLAI

IPC分类号： G06F12/0804 ,  G06F11/14

CPC分类号： G06F12/0804 ,  G06F11/1471 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2212/1032 ,  G06F2212/2022

摘要： Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.

公开(公告)号：US20180322041A1

公开(公告)日：2018-11-08

申请号：US15853429

申请日：2017-12-22

申请人： Silicon Motion, Inc.

发明人： Shen-Ting CHIU

IPC分类号： G06F12/02 ,  G06F9/30 ,  G06F11/07

CPC分类号： G06F12/0246 ,  G06F9/3004 ,  G06F11/073 ,  G06F2212/2022 ,  G06F2212/7201 ,  G11C29/52

摘要： A data-downloading technique for a data storage device before soldering the data storage device into a product. The data storage device uses a flash memory to provide first-type blocks (using single level cells) and second-type blocks (using multi-level cells). Before soldering the data storage device onto a printed circuit board, a controller of the data storage device allocates the first-type blocks to store data from a host. When the allocated number of first-type blocks reaches an upper limit, the controller changes to allocate the second-type blocks to store data from the host. When detecting that the controller has changed to allocate the flash memory to provide the second-type blocks to receive data from the host, the controller returns a fail message to the host to indicate unreliable write operations prior to soldering.

公开(公告)号：US20180239697A1

公开(公告)日：2018-08-23

申请号：US15439779

申请日：2017-02-22

申请人： CNEXLABS, Inc. a Delaware Corporation

发明人： Yiren Ronnie Huang ,  David Hansen Geddes

IPC分类号： G06F12/02 ,  G06F12/109

CPC分类号： G06F12/0246 ,  G06F9/45558 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/1044 ,  G06F2212/151 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7208

摘要： A method and/or apparatus capable of storing information in non-volatile memory with multiple namespaces is disclosed. The method or apparatus, in one aspect, includes a translation table, a global LBA table, and a FTL table wherein the translation table is also known as namespace translation table. The translation table, in one example, includes multiple entries wherein each entry stores translated information relating to translation between an incoming logical block address (“LBA”) with namespace identifiers (“NSIDs”) and a translated LBA (“TR_LBA”). The global LBA table, in one aspect, has multiple global entries, wherein each global entry stores a global LBA base unit generated in response to a TR_LBA. The FTL table contains multiple FTL entries, wherein each FTL entry includes a physical page address (“PPA”) indexed by a global LBA base unit. The apparatus is capable of facilitating memory access based on the PPA.