公开(公告)号：US20150012713A1

公开(公告)日：2015-01-08

申请号：US14380298

申请日：2012-03-02

申请人： William Henry Flanders ,  Ramamoorthy Guru Prasadh ,  Ashok Kumar Tummala ,  Jamshed Jalal ,  Phanindra Kumar Mannava

发明人： William Henry Flanders ,  Ramamoorthy Guru Prasadh ,  Ashok Kumar Tummala ,  Jamshed Jalal ,  Phanindra Kumar Mannava

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F2212/60

摘要： A data processing apparatus (2) comprises a first protocol domain A configured to operate under a write progress protocol and a second protocol domain B configured to operate under a snoop progress protocol. A deadlock condition is detected if a write target address for a pending write request issued from the first domain A to the second domain B is the same as a snoop target address or a pending snoop request issued from the second domain B to the first domain A. When the deadlock condition is detected, a bridge (4) between the domains may issue an early response to a selected one of the deadlocked write and snoop requests without waiting for the selected request serviced. The early response indicates to the domain that issued the selected request that the selected request has been serviced, enabling the other request to be serviced by the issuing domain.

摘要翻译： 数据处理装置（2）包括被配置为在写入进程协议下操作的第一协议域A和被配置为在侦听进程协议下操作的第二协议域B. 如果从第一域A发送到第二域B的待决写入请求的写入目标地址与从第二域B向第一域A发出的窥探目标地址或未决侦听请求相同，则检测到死锁条件 当检测到死锁状况时，域之间的桥（4）可以对所选择的一个死锁写和窥探请求发出早期响应，而不等待所服务的所选择的请求。 早期响应向发出所选择的请求的域指示所选择的请求已经被服务，使得发出域能够服务其他请求。

公开(公告)号：US09372798B2

公开(公告)日：2016-06-21

申请号：US14380298

申请日：2012-03-02

申请人： William Henry Flanders ,  Ramamoorthy Guru Prasadh ,  Ashok Kumar Tummala ,  Jamshed Jalal ,  Phanindra Kumar Mannava

发明人： William Henry Flanders ,  Ramamoorthy Guru Prasadh ,  Ashok Kumar Tummala ,  Jamshed Jalal ,  Phanindra Kumar Mannava

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F2212/60

摘要： A data processing apparatus (2) comprises a first protocol domain A configured to operate under a write progress protocol and a second protocol domain B configured to operate under a snoop progress protocol. A deadlock condition is detected if a write target address for a pending write request issued from the first domain A to the second domain B is the same as a snoop target address or a pending snoop request issued from the second domain B to the first domain A. When the deadlock condition is detected, a bridge (4) between the domains may issue an early response to a selected one of the deadlocked write and snoop requests without waiting for the selected request serviced. The early response indicates to the domain that issued the selected request that the selected request has been serviced, enabling the other request to be serviced by the issuing domain.

摘要翻译： 数据处理装置（2）包括被配置为在写入进程协议下操作的第一协议域A和被配置为在侦听进程协议下操作的第二协议域B. 如果从第一域A发送到第二域B的待决写入请求的写入目标地址与从第二域B向第一域A发出的窥探目标地址或未决侦听请求相同，则检测到死锁条件 当检测到死锁状况时，域之间的桥（4）可以对所选择的一个死锁写和窥探请求发出早期响应，而不等待所服务的所选择的请求。 早期响应向发出所选择的请求的域指示所选择的请求已经被服务，使得发出域能够服务其他请求。

公开(公告)号：US08463960B2

公开(公告)日：2013-06-11

申请号：US13137358

申请日：2011-08-08

申请人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo

发明人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F9/522

摘要： A centralised synchronizing device for determining progress of at least a subset of transaction requests that are transmitted through a data processing system. A system synchronizing request is a request generated by one of the plurality of transaction generating devices and queries progress of a subset of the transaction requests. The synchronizing device includes: at least one port to and from the data processing system; a multicast circuitry configured to output a plurality of synchronizing requests for multicast to at least some of the devices within the data processing system where the requests query the progress of the subset of the transaction requests. Gather circuitry collects responses to the requests confirming that the queried progress has occurred at the respective devices. The gather circuitry determines when responses to all of the requests have been received and outputs a response to the system synchronizing request.

摘要翻译： 一种用于确定通过数据处理系统发送的交易请求的至少一个子集的进度的集中同步装置。 系统同步请求是由多个事务生成设备之一生成的请求，并查询事务请求子集的进度。 所述同步装置包括：至少一个端口和从所述数据处理系统; 多路广播电路被配置为向所述数据处理系统内的至少一些设备输出多播同步请求，其中所述请求查询所述事务请求的子集的进度。 收集电路收集对请求的响应，确认在相应设备上发生查询进度。 收集电路确定何时接收到对所有请求的响应，并输出对系统同步请求的响应。

公开(公告)号：US20130042034A1

公开(公告)日：2013-02-14

申请号：US13137358

申请日：2011-08-08

申请人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo

发明人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo

IPC分类号： G06F3/00

CPC分类号： G06F9/522

摘要： A centralised synchronising device for determining progress of at least a subset of transaction requests that are transmitted through a data processing system in response to receipt of a system synchronising request, the data processing system having a plurality of devices including a plurality of transaction request generating devices for generating the transaction requests and a plurality of recipient devices for receiving the transaction requests, the synchronising device and at least one interconnect for interconnecting at least some of the devices; wherein the system synchronising request comprising a request generated by one of the plurality of transaction generating devices and querying progress of the at least a subset of the transaction requests; the synchronising device comprising: at least one port for receiving requests from, and outputting requests and responses to, the data processing system; multicast circuitry configured to generate a plurality of synchronising requests in response to receipt of the system synchronising request and to output the plurality of synchronising requests for multicast to at least some of the devices within the data processing system, the synchronising requests querying the progress of the at least subset of the transaction requests at each of the respective devices; gather circuitry for collecting responses to the plurality of synchronising requests the responses confirming the queried progress has occurred at the respective device, the gather circuitry being configured to determine when responses to all of the plurality of synchronising requests have been received and in response to determining that all of the responses have been received to output a response to the system synchronising request.

摘要翻译： 一种用于确定响应于系统同步请求的接收而通过数据处理系统发送的交易请求的至少一个子集的进度的集中同步装置，所述数据处理系统具有包括多个交易请求生成装置 用于生成所述事务请求和用于接收所述事务请求的多个接收方设备，所述同步设备和用于互连所述设备中的至少一些的至少一个互连; 其中所述系统同步请求包括由所述多个交易产生装置之一生成的请求，并查询所述交易请求的所述至少一个子集的进度; 所述同步装置包括：至少一个端口，用于从所述数据处理系统接收请求并向所述数据处理系统输出请求和响应; 多播电路，被配置为响应于接收到所述系统同步请求而生成多个同步请求，并且将所述多个同步请求输出到所述数据处理系统内的至少一些设备，所述同步请求询问所述进程 在每个相应设备的交易请求的至少子集; 收集用于收集对多个同步请求的响应的电路，确认所询问的进度的响应已经在相应的设备处发生，所述收集电路被配置为确定何时已经接收到对所有多个同步请求的所有响应，并响应于确定 已收到所有响应以输出对系统同步请求的响应。

公开(公告)号：US08490107B2

公开(公告)日：2013-07-16

申请号：US13137362

申请日：2011-08-08

申请人： Jamshed Jalal ,  Mark David Werkheiser ,  Brett Stanley Feero ,  Michael Alan Filippo ,  Ramamoorthy Guru Prasadh ,  Phanindra Kumar Mannava

发明人： Jamshed Jalal ,  Mark David Werkheiser ,  Brett Stanley Feero ,  Michael Alan Filippo ,  Ramamoorthy Guru Prasadh ,  Phanindra Kumar Mannava

IPC分类号： G06F9/46 ,  G06F15/16 ,  G06F15/173

CPC分类号： H04L47/821 ,  H04L47/70 ,  H04L47/805

摘要： An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.

摘要翻译： 集成电路2包括经由基于环的互连30与共享高速缓存22,24进行通信的多个事务源6,8,10,12,14,16,18,20，每个具有相关联的POC / POS 30,34，以及 作为请求维修电路。 请求服务电路具有可被分配给不同事务的一组处理资源36。 可以动态地或静态地分配这些处理资源。 可以根据选择算法进行静态分配。 该选择算法可以使用服务质量值/优先级作为其输入变量之一。 还可以定义饥饿比例，使得如果饥饿分配太长时间，则强制选择较低的优先级。 可以在服务质量值和优先级之间进行可编程映射。 分配给每个优先级的处理资源的最大数量也可以被编程。

公开(公告)号：US20130042077A1

公开(公告)日：2013-02-14

申请号：US13137356

申请日：2011-08-08

申请人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo

发明人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F9/38 ,  G06F2212/621

摘要： A data processing system that manages data hazards at a coherency controller and not at an initiator device is disclosed. The data processing system process write requests in a two part form, such that a first part is transmitted and when the coherency controller has space to accept data it responds to the first part and the data and state of the data prior to the write are sent as a second part of the write request. When there are copending reads and writes to the same address the writes are stalled by the coherency controller by not responding to the first part of the write and the initiator device proceeds to process any snoop requests received to the address of the write regardless of the fact that the write is pending. When the pending read has completed the coherency controller will respond to the first part of the write and the initiator device will complete the write by sending the data and an indicator of the state of the data following the snoop. The coherency controller can then avoid any potential data hazard using this information to update memory as required.

摘要翻译： 公开了一种在一致性控制器而不是发起者设备处理数据危害的数据处理系统。 数据处理系统以两部分的形式处理写入请求，使得发送第一部分，并且当一致性控制器具有接收对第一部分作出响应的数据的空间以及写入之前的数据和数据的状态发送时 作为写请求的第二部分。 当对相同地址进行共同读取和写入时，写入由相关性控制器停止，不响应写入的第一部分，并且启动器设备继续处理接收到写入地址的任何窥探请求，而不考虑事实 写入待处理。 当等待读取完成后，一致性控制器将响应写入的第一部分，发起者设备将通过发送数据和监听后的数据状态的指示符来完成写入。 一致性控制器可以避免任何潜在的数据危害，使用此信息根据需要更新内存。

公开(公告)号：US08949547B2

公开(公告)日：2015-02-03

申请号：US13137356

申请日：2011-08-08

申请人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo

发明人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo

IPC分类号： G06F12/08 ,  G06F13/14 ,  G06F9/38

CPC分类号： G06F12/0831 ,  G06F9/38 ,  G06F2212/621

摘要： A data processing system that manages data hazards at a coherency controller and not at an initiator device is disclosed. Write requests are processed in a two part form, such that a first part is transmitted and when the coherency controller has space to accept data, the data and a state of the data prior to a write are sent as a second part of a write request. When there are copending reads and writes to the same address, writes are stalled by not responding to the first part of a write request and snoop requests received to the address are processed regardless of the fact that the write is pending. When the pending read has completed, the coherency controller will respond to the first part of the write request and the initiator device will complete the write by sending the data and a state indicator following the snoop.

摘要翻译： 公开了一种在一致性控制器而不是发起者设备处理数据危害的数据处理系统。 写入请求以两部分的形式进行处理，使得第一部分被传送，并且当一致性控制器具有接受数据的空间时，写入之前的数据和数据的状态作为写入请求的第二部分被发送 。 当对相同地址进行共同读取和写入时，通过不响应写入请求的第一部分来停止写入，并且处理接收到地址的侦听请求，而不管写入挂起的事实如何。 当挂起的读取完成时，一致性控制器将响应写入请求的第一部分，并且发起者设备将通过发送数据和跟随侦听器的状态指示符来完成写入。

公开(公告)号：US08463958B2

公开(公告)日：2013-06-11

申请号：US13137363

申请日：2011-08-08

申请人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo ,  Bruce James Mathewson ,  Timothy Charles Mace

发明人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo ,  Bruce James Mathewson ,  Timothy Charles Mace

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F13/364 ,  G06F13/1605

摘要： Initiator devices for generating transaction requests and recipient devices for receiving them are disclosed. The recipient devices accept transaction requests where there is available buffer storage for the transaction request. If there is no storage space available an acknowledgement signal generator generates and outputs a reject acknowledgement signal indicating a request has been received but has not been accepted by the recipient device. A credit generator can reserve at least one available storage location in the buffer and generate a credit grant for an initiator device that sent one of the transaction requests that was not accepted by the recipient device. The credit grant indicates to the initiator device that there is at least one reserved storage location, such that a subsequent transaction request from the initiator device will be accepted by the recipient device. Thus, the initiator device may not transmit the transaction request again until it has received the credit grant, whereupon it may transmit it along with a credit grant indicator such that it is sure that it will be accepted.

公开(公告)号：US20130042252A1

公开(公告)日：2013-02-14

申请号：US13137360

申请日：2011-08-08

申请人： Jamshed Jalal ,  Mark David Werkheiser ,  Brett Stanley Feero ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo ,  Phanindra Kumar Mannava

发明人： Jamshed Jalal ,  Mark David Werkheiser ,  Brett Stanley Feero ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo ,  Phanindra Kumar Mannava

IPC分类号： G06F9/50

CPC分类号： G06F13/374

摘要： An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.

摘要翻译： 集成电路2包括经由基于环的互连30与共享高速缓存22,24进行通信的多个事务源6,8,10,12,14,16,18,20，每个具有相关联的POC / POS 30,34，以及 作为请求维修电路。 请求服务电路具有可被分配给不同事务的一组处理资源36。 可以动态地或静态地分配这些处理资源。 可以根据选择算法进行静态分配。 该选择算法可以使用服务质量值/优先级作为其输入变量之一。 还可以定义饥饿比例，使得如果饥饿分配太长时间，则强制选择较低的优先级。 可以在服务质量值和优先级之间进行可编程映射。 分配给每个优先级的处理资源的最大数量也可以被编程。

公开(公告)号：US20130042249A1

公开(公告)日：2013-02-14

申请号：US13137362

申请日：2011-08-08

申请人： Jamshed Jalal ,  Mark David Werkheiser ,  Brett Stanley Feero ,  Michael Alan Filippo ,  Ramamoorthy Guru Prasadh ,  Phanindra Kumar Mannava

发明人： Jamshed Jalal ,  Mark David Werkheiser ,  Brett Stanley Feero ,  Michael Alan Filippo ,  Ramamoorthy Guru Prasadh ,  Phanindra Kumar Mannava

IPC分类号： G06F9/46

CPC分类号： H04L47/821 ,  H04L47/70 ,  H04L47/805

摘要： An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.