公开(公告)号：US07701752B2

公开(公告)日：2010-04-20

申请号：US12266650

申请日：2008-11-07

申请人： Wing K. Luk ,  Brian L. Li

发明人： Wing K. Luk ,  Brian L. Li

IPC分类号： G11C11/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C8/16 ,  G11C11/403 ,  G11C11/405 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2211/4065

摘要： A dynamic random access memory circuit is provided, having at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to the at least one read bit line and configured to generate an output signal, a refresh bypass device operatively associated with the sense amplifier and the at least one write bit line so as to selectively pass the output signal to the at least one write bit line, and a write-read bypass device operatively coupled to the at least one write bit line and the at least one read bit line and configured to selectively pass a write signal from a write bit line signal point along the at least one write bit line to a read bit line signal point along the at least one read bit line for output to a data output. the output signal is selectively passed to the at least one write bit line. The write signal is selectively passed from the write bit line signal point along the at least one write bit line to the read bit line signal point along the at least one read bit line for output to the data output.

摘要翻译： 提供了一种动态随机存取存储器电路，其具有至少一个写位线，至少一个读位线，电容存储器件，可操作地耦合到电容存储器件和至少一个写位线的写入存取器件， 感测放大器，其可操作地耦合到所述至少一个读取位线并且被配置为产生输出信号，与所述读出放大器和所述至少一个写入位线可操作地相关联的刷新旁路装置，以选择性地将所述输出信号传递到所述至少一个 一个写入位线以及可操作地耦合到所述至少一个写入位线和所述至少一个读取位线的写入读取旁路器件，并被配置为沿着所述至少一个读取位线选择性地传递来自写入位线信号点的写入信号 将位线沿着至少一个读位线写入读位线信号点，以输出到数据输出。 输出信号被选择性地传递到至少一个写位线。 写入信号从写入位线信号点沿着至少一个写位线选择性地沿着至少一个读位线传递到读位线信号点，以输出到数据输出端。