公开(公告)号：US12051457B2

公开(公告)日：2024-07-30

申请号：US17664465

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chieh Liu ,  Jui-Jen Wu ,  Win-San Khwa ,  Yi-Lun Lu ,  Meng-Fan Chang

IPC: G11C11/34 ,  G11C11/405

CPC classification number: G11C11/405

Abstract: A device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The device further includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to a data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.

公开(公告)号：US20240134605A1

公开(公告)日：2024-04-25

申请号：US18278451

申请日：2022-02-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Kazuki TSUDA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU

IPC: G06F7/523 ,  G06F7/50 ,  G09G3/3208 ,  G11C11/405 ,  H10B12/00 ,  H10K59/121

CPC classification number: G06F7/523 ,  G06F7/50 ,  G09G3/3208 ,  G11C11/405 ,  H10B12/00 ,  H10K59/1213 ,  H10K59/1216

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a cell array performing a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit from which first data is input to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, the first region is supplied with the t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs the t-th second data according to the product-sum operation of the first layer to the second circuit. In the first period, the second region is supplied with the (t+1)-th first data from the first circuit and outputs the (t+1)-th second data according to the product-sum operation of the second layer to the first circuit.

公开(公告)号：US11963374B2

公开(公告)日：2024-04-16

申请号：US17582092

申请日：2022-01-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H10B99/00 ,  G11C11/405 ,  G11C16/04 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/16 ,  H01L29/24 ,  H01L29/786 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L21/822 ,  H01L27/06 ,  H01L29/78 ,  H10B12/00

CPC classification number: H10B99/00 ,  G11C11/405 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/11803 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/24 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  G11C2211/4016 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/7833 ,  H10B12/00

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US20240120340A1

公开(公告)日：2024-04-11

申请号：US18538161

申请日：2023-12-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI

IPC: H01L27/105 ,  G11C11/405 ,  G11C16/04 ,  H01L21/02 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70

CPC classification number: H01L27/105 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/02664 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/1225 ,  H01L29/06 ,  H01L29/7869 ,  H01L29/78693 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L27/0207

Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

公开(公告)号：US20180174647A1

公开(公告)日：2018-06-21

申请号：US15383100

申请日：2016-12-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kei Takahashi ,  Takayuki Ikeda ,  Naoaki Tsutsui

IPC: G11C11/419 ,  H01L27/12 ,  H01L27/11

CPC classification number: G11C11/419 ,  G09G3/36 ,  G09G5/00 ,  G11C7/02 ,  G11C11/405 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4085 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/24 ,  H01L29/7851 ,  H01L29/7869

Abstract: Objects are to provide a semiconductor device with a novel structure, to provide a semiconductor device with high resistance to noise, to provide a semiconductor device with a small chip area, and to provide a semiconductor device with low power consumption. In a memory cell included in a frame memory, a transistor containing an oxide semiconductor and a transistor containing silicon are used in combination to retain charge, whereby data is retained. In this structure, turning off the transistor containing an oxide semiconductor can prevent data fluctuations even if power noise through a wiring is generated.

公开(公告)号：US10002660B2

公开(公告)日：2018-06-19

申请号：US15632555

申请日：2017-06-26

Applicant: Bar-Ilan University

Inventor： Robert Giterman ,  Adam Teman ,  Pascal Meinerzhagen ,  Andreas Burg ,  Alexander Fish

IPC: G11C5/06 ,  G11C11/41 ,  G11C11/403 ,  G11C11/4097 ,  G11C5/02 ,  G11C7/10 ,  H01L27/11 ,  G11C8/14 ,  G11C8/16 ,  G11C11/405

CPC classification number: G11C11/41 ,  G11C5/025 ,  G11C5/063 ,  G11C7/10 ,  G11C8/14 ,  G11C8/16 ,  G11C11/403 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/1104

Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.

公开(公告)号：US20180102365A1

公开(公告)日：2018-04-12

申请号：US15729532

申请日：2017-10-10

Applicant: IMEC vzw

Inventor： Jan Van Houdt ,  Julien Ryckaert ,  Hyungrock Oh

IPC: H01L27/108 ,  H01L21/8254 ,  G11C11/405

CPC classification number: H01L27/108 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  H01L21/8254 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/10805 ,  H01L28/60

Abstract: The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.

公开(公告)号：US20180047730A1

公开(公告)日：2018-02-15

申请号：US15728797

申请日：2017-10-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Keitaro IMAI ,  Jun KOYAMA

IPC: H01L27/108 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8258 ,  H01L27/06 ,  G11C11/404 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L27/10802 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/7869

Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10−13 A or less.

公开(公告)号：US09870827B2

公开(公告)日：2018-01-16

申请号：US15359017

申请日：2016-11-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takashi Nakagawa ,  Hiroki Inoue ,  Fumika Akasawa ,  Yoshiyuki Kurokawa

IPC: G11C16/04 ,  G11C11/34 ,  G11C16/10 ,  H01L27/12 ,  H01L27/146

CPC classification number: G11C16/10 ,  G11C7/1006 ,  G11C7/16 ,  G11C8/12 ,  G11C11/405 ,  G11C11/4087 ,  G11C16/0466 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/14616 ,  H01L27/14636 ,  H01L27/14643

Abstract: A semiconductor device with an arithmetic processing function is provided. The semiconductor device includes a first circuit and a second circuit each having a function of performing one-dimensional discrete cosine transform. By directly inputting output data of the first circuit to the second circuit, two-dimensional discrete cosine transform can be performed immediately. A memory cell array included in the first circuit is divided into a plurality of memory blocks. In the case where a selection transistor is provided in the memory block, data processing can be performed in each memory block.

公开(公告)号：US09823689B2

公开(公告)日：2017-11-21

申请号：US15092114

申请日：2016-04-06

Applicant: Laurence H. Cooke

Inventor： Laurence H. Cooke

IPC: G06F1/12 ,  G06F9/30 ,  G06F15/78 ,  G06F15/80 ,  G11C11/405 ,  G06F1/06

CPC classification number: G06F1/12 ,  G06F1/06 ,  G06F9/30014 ,  G06F9/30032 ,  G06F15/7867 ,  G06F15/8015 ,  G11C11/405

Abstract: A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit.