公开(公告)号：US20240363616A1

公开(公告)日：2024-10-31

申请号：US18769004

申请日：2024-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hidehiro FUJIWARA ,  Sahil Preet SINGH ,  Chih-Yu LIN ,  Hsien-Yu PAN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC: H01L27/02 ,  G11C5/06 ,  G11C7/18 ,  H01L23/522 ,  H10B10/00

CPC classification number: H01L27/0207 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H10B10/12

Abstract: A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer.

公开(公告)号：US12112829B2

公开(公告)日：2024-10-08

申请号：US17575397

申请日：2022-01-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Ying Lee ,  Chia-En Huang ,  Meng-Sheng Chang

IPC: G11C7/14 ,  G11C7/18 ,  H01L25/065 ,  H10B12/00

CPC classification number: G11C7/14 ,  G11C7/18 ,  H01L25/0655 ,  H10B12/056 ,  H10B12/36

Abstract: A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.

公开(公告)号：US12096636B2

公开(公告)日：2024-09-17

申请号：US17479573

申请日：2021-09-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  Fei Zhou

IPC: H10B43/35 ,  G11C7/18 ,  H01L23/48 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C7/18 ,  H01L23/481 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

公开(公告)号：US12069858B2

公开(公告)日：2024-08-20

申请号：US18194258

申请日：2023-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Dong-Sik Lee

IPC: H10B41/20 ,  G11C7/18 ,  G11C16/08 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/46 ,  H10B41/48 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B41/46 ,  G11C7/18 ,  G11C16/08 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/20 ,  H10B41/48 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

公开(公告)号：US12027412B2

公开(公告)日：2024-07-02

申请号：US17814626

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L21/762 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

CPC classification number: H01L21/76237 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

公开(公告)号：US12014770B2

公开(公告)日：2024-06-18

申请号：US17649342

申请日：2022-01-28

Applicant: R&D 3 LLC

Inventor： Ravindraraj Ramaraju

IPC: G11C7/14 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/56 ,  G11C16/30 ,  G11C8/16 ,  G11C11/405 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/14 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4045 ,  G11C11/4091 ,  G11C11/565 ,  G11C16/30 ,  G11C8/16 ,  G11C11/405 ,  G11C11/4094 ,  G11C2207/2254

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

公开(公告)号：US20240178134A1

公开(公告)日：2024-05-30

申请号：US18437549

申请日：2024-02-09

Applicant: Lodestar Licensing Group LLC

Inventor： Darwin A. Clampitt ,  Roger W. Lindsay ,  Jeffrey D. Runia ,  Matthew Holland ,  Chamunda N. Chamunda

IPC: H01L23/522 ,  G11C7/18 ,  G11C8/14 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5226 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device comprises a stack structure, a stadium structure within the stack structure, and conductive contact structures. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each of the tiers comprises one of the conductive structures and one of the insulative structures. The stadium structure comprises a forward staircase structure having steps comprising edges of the tiers, and a reverse staircase structure opposing the forward staircase structure and having additional steps comprising additional edges of the tiers. The conductive contact structures vertically extend to upper vertical boundaries of at least some of the conductive structures of the stack structure at the steps of the forward staircase structure and the additional steps of the reverse staircase structure, and are each integral and continuous with one of the conductive structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20240172431A1

公开(公告)日：2024-05-23

申请号：US18425996

申请日：2024-01-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Johann ALSMEIER ,  Lito De La RAMA ,  Masaaki HIGASHITANI ,  Koichi MATSUNO ,  Marika GUNJI-YONEOKA ,  Makoto KOTO ,  Hisakazu OTOI ,  Masanori TSUTSUMI

IPC: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/06 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/0653 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a plurality of source layers, where the electrically conductive layers include word lines and source-side select gate electrodes which are located between the plurality of source layers and the word lines in a vertical direction, groups of memory openings vertically extending through the alternating stack, and groups of memory opening fill structures located in the groups of memory openings. The plurality of source layers are laterally spaced apart and electrically isolated from each other, and each respective one of the plurality of source layers contacts at least one respective group of the groups of memory opening fill structures.

公开(公告)号：US11942177B2

公开(公告)日：2024-03-26

申请号：US17572370

申请日：2022-01-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Ta Yu ,  Chia-En Huang ,  Sai-Hooi Yeong ,  Yih Wang ,  Yi-Ching Liu

IPC: G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14

CPC classification number: G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14

Abstract: One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.

公开(公告)号：US11889684B2

公开(公告)日：2024-01-30

申请号：US16951325

申请日：2020-11-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori Tsutsumi ,  Shinsuke Yada ,  Mitsuteru Mushiga ,  Akio Nishida ,  Hiroyuki Ogawa ,  Teruo Okina

IPC: H10B41/27 ,  H01L29/06 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/0653 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over at least one source layer, and groups of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source-side select gate electrodes can be laterally spaced apart by source-select-level dielectric isolation structures. Alternatively or additionally, the at least one source layer may include a plurality of source layers. A group of memory opening fill structures can be selected by selecting a source layer and/or by selecting a source-level electrically conductive layer.