公开(公告)号：US20230222026A1

公开(公告)日：2023-07-13

申请号：US17574340

申请日：2022-01-12

Applicant: XILINX, INC.

Inventor： Sarosh I. AZAD ,  Aditi R. GANESAN

IPC: G06F11/07 ,  G06F11/10

CPC classification number: G06F11/0751 ,  G06F11/1004 ,  G06F11/0772

Abstract: An integrated circuit (IC) device for detecting errors within a register, the IC device includes registers and parity checking circuitry. The parity checking circuitry is coupled to the registers and comprises a first parity circuitry, a second parity circuit, and error detection circuitry. The first parity circuit receives first register values from the registers and determine a first value from the first register values. The second parity circuit is receives second register values from the registers and determines a second value from the second register values. The error detection circuitry compares the first value and the second value to detect a first error within the registers, and output an error signal indicating the first error.

公开(公告)号：US20230376389A1

公开(公告)日：2023-11-23

申请号：US17746843

申请日：2022-05-17

Applicant: XILINX, INC.

Inventor： David TRAN ,  Aditi R. GANESAN ,  Anurag GOYAL

IPC: G06F11/16 ,  H03L7/081

CPC classification number: G06F11/1679 ,  H03L7/0814

Abstract: Methods and systems to detect a metastable condition and suppress/mask a signal during the metastable condition. The metastable condition may arise from asynchronous sampling. Techniques disclosed herein may be configured to enable asynchronous lock-stepping, where outputs of redundant circuit blocks of a first clock domain are received at input nodes of a second clock domain. In the second clock domain, logic states at the input nodes are compared to detect errors, and results of the comparison are masked during transitions at the input nodes. Masking may be constrained to situations where logic states at the input nodes differ.