公开(公告)号：US20230085149A1

公开(公告)日：2023-03-16

申请号：US17477185

申请日：2021-09-16

Applicant: XILINX, INC.

Inventor： Pramod BHARDWAJ ,  Sarosh I. AZAD ,  Wern-Yan KOE ,  Amitava MAJUMDAR

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/28

Abstract: In one example, an integrated circuit (IC) is provided that includes data circuitry and a processing circuitry. The data circuitry is configured to provide data to be transferred to a different circuitry within the IC or to an external IC. The processing circuitry is configured to: read the data provided by the data circuitry before it is transferred to the different circuitry or the external IC; calculate a first signature for the data; attach the first signature to the data; calculate, after transferring the data to the different circuitry or the external IC, a second signature for the data; extract the first signature corresponding to the data; compare the first signature to the second signature; and generate a signal based on a comparison of the first signature to the second signature.

公开(公告)号：US20240274218A1

公开(公告)日：2024-08-15

申请号：US18109744

申请日：2023-02-14

Applicant: XILINX, INC.

Inventor： David TRAN ,  Federico VENINI ,  Sarosh I. AZAD

IPC: G11C29/52 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C29/022

Abstract: Embodiments herein describe a memory system with a data width (W) that is split into N separate memories each of narrower width W/N. To protect a write enable (WE) signal, the WE signal is toggled and then stored in each of the N memories. For example, toggle circuits can have states that toggle each time the WE signal goes high, indicated that a received data word should be stored in the N memories. A fault on the WE input to any of the N memories results in its stored toggle bit being different from the toggle bits stored in the other N memories. This condition can then be detected upon any subsequent read by checking whether the toggled bits are equal. The memory system can also protect the address and control signals by generating parity bits that are stored in the N memories.

公开(公告)号：US20230222026A1

公开(公告)日：2023-07-13

申请号：US17574340

申请日：2022-01-12

Applicant: XILINX, INC.

Inventor： Sarosh I. AZAD ,  Aditi R. GANESAN

IPC: G06F11/07 ,  G06F11/10

CPC classification number: G06F11/0751 ,  G06F11/1004 ,  G06F11/0772

Abstract: An integrated circuit (IC) device for detecting errors within a register, the IC device includes registers and parity checking circuitry. The parity checking circuitry is coupled to the registers and comprises a first parity circuitry, a second parity circuit, and error detection circuitry. The first parity circuit receives first register values from the registers and determine a first value from the first register values. The second parity circuit is receives second register values from the registers and determines a second value from the second register values. The error detection circuitry compares the first value and the second value to detect a first error within the registers, and output an error signal indicating the first error.

公开(公告)号：US20240111693A1

公开(公告)日：2024-04-04

申请号：US17957418

申请日：2022-09-30

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD ,  Sarosh I. AZAD ,  Pramod BHARDWAJ ,  Yanran CHEN ,  James MURRAY

IPC: G06F13/16 ,  G06F11/07

CPC classification number: G06F13/1631 ,  G06F11/0772 ,  G06F13/1668

Abstract: Techniques to provide transaction redundancy in an IC include receiving an original memory access request directed to a first memory aperture, constructing a redundant memory access directed to a second memory aperture, and selectively returning a response of the first or second memory aperture to an originator based on contents of the responses. For a write operation, if acknowledgement indicators of the responses indicate success, a response is returned to the originator. For a read operation, if acknowledgement indicators of the responses indicate success and data returned in the response match one another, a response is returned to the originator. If the acknowledgement indicators indicate success, but the data does not match, a retry of the original and redundant read requests is initiated. If any of the acknowledgement indicators do not indicate success, an error is declared. In a mixed-criticality embodiment, the redundant memory access request may be constructed selectively.

公开(公告)号：US20230059517A1

公开(公告)日：2023-02-23

申请号：US17405854

申请日：2021-08-18

Applicant: XILINX, INC.

Inventor： Sarosh I. AZAD ,  Benson CHAU ,  Tomai KNOPP

IPC: H03K5/02 ,  H03K23/60 ,  H03K19/173 ,  H03K19/20

Abstract: An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.