公开(公告)号：US20230335510A1

公开(公告)日：2023-10-19

申请号：US17724063

申请日：2022-04-19

Applicant: XILINX, INC.

Inventor： Po-Wei CHIU ,  Tzu-No CHEN ,  Hong SHI ,  Li-Sheng WENG ,  Young Soo LEE

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01L23/645 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: Disclosed herein is a chip package and method for fabricating the same are provided that includes a redistribution layer (RDL) with a plurality of loop and void structures. The chip package includes an integrated circuit (IC) die, and a package substrate. The RDL is disposed between the IC die and the package substrate. The RDL has RDL circuitry that connects the IC die to the package substrate. The RDL circuitry includes a first coil formed in a first metal layer and a second coil formed in a second metal layer. A first end of the second coil is coupled to a second end of the first coil by a first via. A second end of the second coil is the IC die.