公开(公告)号：US20220415788A1

公开(公告)日：2022-12-29

申请号：US17357087

申请日：2021-06-24

Applicant: XILINX, INC.

Inventor： Zhaoyin Daniel WU ,  Parag UPADHYAYA ,  Hong SHI

IPC: H01L23/522 ,  H01Q1/22

Abstract: A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.

公开(公告)号：US20240071958A1

公开(公告)日：2024-02-29

申请号：US17896972

申请日：2022-08-26

Applicant: XILINX, INC.

Inventor： Hong SHI ,  Li-Sheng WENG ,  Frank Peter LAMBRECHT ,  Jing JING ,  Shuxian WU

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/645 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/24225 ,  H01L2224/73209 ,  H01L2924/1427 ,  H01L2924/30107

Abstract: A chip package and method for fabricating the same are provided that includes embedded off-die inductors coupled in series. One of the off-die inductors is disposed in a redistribution layer formed on a bottom surface of an integrated circuit (IC) die. The other of the series connected off-die inductors is disposed in a substrate of the chip package. The substrate may be either an interposer or a package substrate.

公开(公告)号：US20230335510A1

公开(公告)日：2023-10-19

申请号：US17724063

申请日：2022-04-19

Applicant: XILINX, INC.

Inventor： Po-Wei CHIU ,  Tzu-No CHEN ,  Hong SHI ,  Li-Sheng WENG ,  Young Soo LEE

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01L23/645 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: Disclosed herein is a chip package and method for fabricating the same are provided that includes a redistribution layer (RDL) with a plurality of loop and void structures. The chip package includes an integrated circuit (IC) die, and a package substrate. The RDL is disposed between the IC die and the package substrate. The RDL has RDL circuitry that connects the IC die to the package substrate. The RDL circuitry includes a first coil formed in a first metal layer and a second coil formed in a second metal layer. A first end of the second coil is coupled to a second end of the first coil by a first via. A second end of the second coil is the IC die.

公开(公告)号：US20230253380A1

公开(公告)日：2023-08-10

申请号：US17669252

申请日：2022-02-10

Applicant: XILINX, INC.

Inventor： Li-Sheng WENG ,  Suresh RAMALINGAM ,  Hong SHI

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L24/24 ,  H01L2224/24265 ,  H01L2924/19103 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2224/244 ,  H01L2224/24226

Abstract: A chip package and method for fabricating the same are provided that includes a near-die integrated passive device. The near-die integrated passive device is disposed between a package substrate and an integrated circuit die of a chip package. Some non-exhaustive examples of an integrated passive device that may be disposed between the package substrate and the integrated circuit die include a resistor, a capacitor, an inductor, a coil, a balum, or an impedance matching element, among others.

公开(公告)号：US20210366873A1

公开(公告)日：2021-11-25

申请号：US16880811

申请日：2020-05-21

Applicant: XILINX, INC.

Inventor： Jaspreet Singh GANDHI ,  Suresh RAMALINGAM ,  William E. ALLAIRE ,  Hong SHI ,  Kerry M. PIERCE

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.