公开(公告)号：US10797727B1

公开(公告)日：2020-10-06

申请号：US16137927

申请日：2018-09-21

Applicant: Xilinx, Inc.

Inventor： Richard L. Walke ,  Andrew Dow ,  Andrew M. Whyte ,  Nihat E. Tunali

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/39

Abstract: A decoder circuit includes a low-density parity-check (LDPC) repository to store parity-check information associated with one or more LDPC codes and an LDPC code configurator to receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and to update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The decoder circuit further includes an LDPC decoder circuitry configurable, based on control signals, to perform LDPC decoding of codewords or LDPC encoding of information using the parity-check information from the LDPC repository.

公开(公告)号：US10963746B1

公开(公告)日：2021-03-30

申请号：US16247301

申请日：2019-01-14

Applicant: Xilinx, Inc.

Inventor： Andrew M. Whyte

IPC: G06K9/62 ,  G06K9/00 ,  G06N3/04

Abstract: Embodiments herein describe, when executing an average pooling operation in a neural network, scaling input operands before performing an accumulate operation. Performing average pooling in a neural network averages the values in each face of a 3D volume, thereby downsampling or subsampling the data. This can be performed by adding all the values in a face and then dividing the total accumulated value by the total values in the face. However, the order of operations in a multiply-accumulator (MAC) is reversed from the order of operations for performing average pooling. To more efficiently use the MAC, the order of operations when performing average pooling is reversed so that determining the average value for a face can be performed on a single MAC. To do so, the values in the face are first scaled by a multiplier before being summed by an accumulator.

公开(公告)号：US10474390B1

公开(公告)日：2019-11-12

申请号：US15586723

申请日：2017-05-04

Applicant: Xilinx, Inc.

Inventor： Andrew M. Whyte

IPC: G06F3/06 ,  G06F12/06

Abstract: A circuit includes a memory and an address generator configured to generate a write address signal and a read address signal, where the write address signal has a first delay relative to the read address signal. The memory is configured to receive a first plurality of write addresses, from the write address signal, including a first plurality of addresses of the memory in a first order, and write, to the first plurality of write addresses, a first plurality of data words during a first time period. The memory is further configured to receive a first plurality of read addresses, from the read address signal, including the first plurality of addresses in a second order, and read, from the first plurality of read addresses, the first plurality of data words during a second time period. The first and second time periods partially overlap. The first order may be one of a natural order and a modified order, with the second order being the other of the natural order and the modified order, and the modified order may be one of a bit-reversed order and a digit-reversed order. The memory may have different write modes, and may be a read-before-write memory or a write-before-read memory.