公开(公告)号：US10727869B1

公开(公告)日：2020-07-28

申请号：US15938760

申请日：2018-03-28

Applicant: Xilinx, Inc.

Inventor： Richard L. Walke ,  Andrew Dow

IPC: H03M13/00 ,  H03M13/11

Abstract: A decoder circuit includes an input to receive a first codeword encoded based on a quasi-cyclic low-density parity-check (QC LDPC) code and a plurality of memory banks to store the received codeword. Each column of the received codeword is assigned to one of the plurality of memory banks based at least in part on an order of the plurality of columns in the received codeword. A first reordering stage is to change the memory bank assignment for one or more of the plurality of columns by reordering the columns in the received codeword. An LDPC decoder is to decode the reordered codeword stored in the plurality of memory banks based at least in part on the QC LDPC code. A second reordering stage is to output the decoded codeword from the plurality of memory banks based at least in part on an order of the columns in the first codeword.

公开(公告)号：US11075650B1

公开(公告)日：2021-07-27

申请号：US16666599

申请日：2019-10-29

Applicant: Xilinx, Inc.

Inventor： Andrew Dow ,  Richard L. Walke

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/07

Abstract: A decoder circuit includes an input to receive a first codeword encoded based on a quasi-cyclic low-density parity-check (QC LDPC) code. The first codeword includes a sequence of data arranged according to an order of columns in a first parity-check matrix associated with the QC LDPC code. A codeword reordering stage generates a reordered codeword by changing the sequence of the data in the first codeword based at least in part on a size of one or more circulant submatrices in the first parity-check matrix. An LDPC decoder generates a decoded codeword by decoding the reordered codeword based on a second parity-check matrix associated with the QC LDPC code. In some implementations, the second parity-check matrix may comprise a plurality of second circulant submatrices of a different size than the first circulant submatrices.

公开(公告)号：US10797727B1

公开(公告)日：2020-10-06

申请号：US16137927

申请日：2018-09-21

Applicant: Xilinx, Inc.

Inventor： Richard L. Walke ,  Andrew Dow ,  Andrew M. Whyte ,  Nihat E. Tunali

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/39

Abstract: A decoder circuit includes a low-density parity-check (LDPC) repository to store parity-check information associated with one or more LDPC codes and an LDPC code configurator to receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and to update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The decoder circuit further includes an LDPC decoder circuitry configurable, based on control signals, to perform LDPC decoding of codewords or LDPC encoding of information using the parity-check information from the LDPC repository.

公开(公告)号：US10833704B1

公开(公告)日：2020-11-10

申请号：US16217648

申请日：2018-12-12

Applicant: Xilinx, Inc.

Inventor： Richard L. Walke ,  Andrew Dow ,  Zahid Khan

IPC: H03M13/11 ,  H03M13/00 ,  H03M13/37 ,  G06F11/10

Abstract: Low-density parity check (LDPC) decoder circuitry is configured to decode an input codeword using a plurality of circulant matrices of a parity check matrix for an LDPC code. Multiple memory banks are configured to store elements of the input codeword. A memory circuit is configured for storage of an instruction sequence. Each instruction describes for one of the circulant matrices, a corresponding layer and column of the parity check matrix and a rotation. Each instruction includes packing factor bits having a value indicative of a number of instructions of the instruction sequence to be assembled in a bundle of instructions. A bundler circuit is configured to assemble the number of instructions from the memory circuit in a bundle. The bundler circuit specifies one or more no-operation codes (NOPs) in the bundle in response to the value of the packing factor bits and provides the bundle to the decoder circuitry.