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    Low-density parity check decoder using encoded no-operation instructions
    1.
    发明授权
    Low-density parity check decoder using encoded no-operation instructions 有权

    公开(公告)号：US10833704B1

    公开(公告)日：2020-11-10

    申请号：US16217648

    申请日：2018-12-12

    Applicant: Xilinx, Inc.

    Inventor： Richard L. Walke ,  Andrew Dow ,  Zahid Khan

    IPC: H03M13/11 ,  H03M13/00 ,  H03M13/37 ,  G06F11/10

    Abstract: Low-density parity check (LDPC) decoder circuitry is configured to decode an input codeword using a plurality of circulant matrices of a parity check matrix for an LDPC code. Multiple memory banks are configured to store elements of the input codeword. A memory circuit is configured for storage of an instruction sequence. Each instruction describes for one of the circulant matrices, a corresponding layer and column of the parity check matrix and a rotation. Each instruction includes packing factor bits having a value indicative of a number of instructions of the instruction sequence to be assembled in a bundle of instructions. A bundler circuit is configured to assemble the number of instructions from the memory circuit in a bundle. The bundler circuit specifies one or more no-operation codes (NOPs) in the bundle in response to the value of the packing factor bits and provides the bundle to the decoder circuitry.

    System and method for determining bit types for polar encoding and decoding
    4.
    发明授权
    System and method for determining bit types for polar encoding and decoding 有权

    公开(公告)号：US11082067B1

    公开(公告)日：2021-08-03

    申请号：US16592381

    申请日：2019-10-03

    Applicant: XILINX, INC.

    Inventor： Ming Ruan ,  Gordon I. Old ,  Richard L. Walke ,  Zahid Khan

    IPC: H03M13/13 ,  G06F1/03 ,  G06F9/30 ,  H03M13/09

    Abstract: Embodiments described herein provide a code generation mechanism (FIG. 3, 301) in a Polar encoder (FIG. 2, 204) to determine a bit type (FIG. 3, 312) corresponding to each coded bit in the Polar code before sending the data bits for encoding (FIG. 3, 303). For example, each bit in the Polar code is determined to have a bit type of a frozen bit, parity bit, an information bit, or a cyclic redundancy check (CRC) bit based at least on the respective reliability index of the bit from a pre-computed reliability index lookup table (FIG. 4A, 411). In this way, the bit type determination can be completed in one loop by iterating the list of entries in the pre-computed reliability index lookup table.

    Efficient method for packing low-density parity-check (LDPC) decode operations
    5.
    发明授权
    Efficient method for packing low-density parity-check (LDPC) decode operations 有权

    公开(公告)号：US10727869B1

    公开(公告)日：2020-07-28

    申请号：US15938760

    申请日：2018-03-28

    Applicant: Xilinx, Inc.

    Inventor： Richard L. Walke ,  Andrew Dow

    IPC: H03M13/00 ,  H03M13/11

    Abstract: A decoder circuit includes an input to receive a first codeword encoded based on a quasi-cyclic low-density parity-check (QC LDPC) code and a plurality of memory banks to store the received codeword. Each column of the received codeword is assigned to one of the plurality of memory banks based at least in part on an order of the plurality of columns in the received codeword. A first reordering stage is to change the memory bank assignment for one or more of the plurality of columns by reordering the columns in the received codeword. An LDPC decoder is to decode the reordered codeword stored in the plurality of memory banks based at least in part on the QC LDPC code. A second reordering stage is to output the decoded codeword from the plurality of memory banks based at least in part on an order of the columns in the first codeword.

    Log-likelihood ratio processing for linear block code decoding
    6.
    发明授权
    Log-likelihood ratio processing for linear block code decoding 有权

    公开(公告)号：US10484021B1

    公开(公告)日：2019-11-19

    申请号：US15916090

    申请日：2018-03-08

    Applicant: Xilinx, Inc.

    Inventor： Gordon I. Old ,  Richard L. Walke

    IPC: H03M13/45 ,  H03M13/00

    Abstract: Apparatuses and methods relating generally to a decoder. In an apparatus, a control circuit receives first-third sign signals, a partial sum signal, a function select signal, and a carry signal as an input vector to provide an output sign and a vector select. A select generation circuit receives the first and second sign signals and the partial sum signal to provide an add/subtract select signal. A subtractor subtracts from a first absolute value signal a second absolute value signal to provide the third sign signal and a difference signal. Responsive to the add/subtract select signal, an adder/subtractor either adds or subtracts the first absolute value signal to or from the second absolute value signal to provide the carry signal and a sum/difference signal. A multiplexer selects from the first and second absolute value signals, the difference signal, and the sum/difference signal a selected value signal responsive to the vector select.

    Multiplier circuits configurable for real or complex operation
    8.
    发明授权
    Multiplier circuits configurable for real or complex operation 有权

    公开(公告)号：US09778905B1

    公开(公告)日：2017-10-03

    申请号：US14995100

    申请日：2016-01-13

    Applicant: Xilinx, Inc.

    Inventor： Richard L. Walke

    IPC: G06F7/48

    CPC classification number: G06F7/4812

    Abstract: A system includes an integrated circuit coupled to the memory. The integrated circuit is configured to receive first and second complex numbers at one or more data inputs. A first value is determined using a first set of product arrays of a first real number multiplier. A second value is determined using a second set of product arrays of the first real number multiplier and a third set of product arrays of a second real number multiplier. A third value is determined using a fourth set of product arrays of the second real number multiplier. A real value of a first product of the first complex number times a second complex number is determined using the first value and the second value. An imaginary value of the first product is determined using the second value and the third value.

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