公开(公告)号：US09876657B1

公开(公告)日：2018-01-23

申请号：US15451209

申请日：2017-03-06

Applicant: Xilinx, Inc.

Inventor： Charles Jeon ,  Christoph E. Studer ,  Michael Wu ,  Christopher H. Dick

IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49 ,  H04B7/0452

CPC classification number: H04L25/03159 ,  H04B7/0452 ,  H04L25/03012 ,  H04L2025/03426

Abstract: An integrated circuit (IC) includes a downlink unit including an input to receive a first plurality of frequency domain (FD) symbols associated with data symbols for a plurality of users, and an iteration unit to perform a plurality of iterations based on adjustment values. Each iteration includes generating a second plurality of FD symbols by performing a precoding process based on the first plurality of FD symbols, generating a third plurality of time domain (TD) symbols by performing a first modulation process based on the second plurality of FD symbols, generating a fourth plurality of TD symbols by performing a dynamic range reduction process based on absolute values of the third plurality of TD symbols, and updating the adjustment values. The downlink unit further includes a decision unit configured to generate transmit TD symbols for transmission through a channel to the plurality of users.