公开(公告)号：US11461625B1

公开(公告)日：2022-10-04

申请号：US16881612

申请日：2020-05-22

Applicant: Xilinx, Inc.

Inventor： Michael Wu ,  Christopher H. Dick

IPC: G06N3/063 ,  H03M7/30 ,  G06F7/22 ,  G06F7/50 ,  G06F7/523

Abstract: Lossy tensor compression and decompression circuits compress and decompress tensor elements based on the values of neighboring tensor elements. The lossy compression circuit scales each decompressed tensor element of a tile by a scaling factor that is based on the maximum value that can be represented by the number of bits used to represent a compressed tensor element, and the greatest value and least value of the tensor elements of the tile. The lossy decompression circuit performs the inverse of the lossy compression. The compression circuit and decompression circuit have parallel multiplier circuits and parallel adder circuits to perform the lossy compression and lossy decompression, respectively.

公开(公告)号：US09941943B1

公开(公告)日：2018-04-10

申请号：US15160847

申请日：2016-05-20

Applicant: Xilinx, Inc.

Inventor： Michael Wu ,  Christopher H. Dick ,  Christoph E. Studer

IPC: H04B7/02 ,  H04B7/0456 ,  H04B7/0413 ,  H04L25/02

CPC classification number: H04L25/0242 ,  H04B7/0413

Abstract: A system includes an integrated circuit configured to communicating data in a channel. A channel matrix for the channel including a plurality of columns is received. A preprocessing step is performed, using a preprocessing unit, to compute a plurality of preprocessed column values corresponding to respective columns. An update step is performed, using an update unit, to update an estimation vector using a plurality of outer-loop iterations of an outer loop. Each outer-loop iteration updates the estimation vector using the plurality of preprocessed column values. An access link process is performed using the estimation vector.

公开(公告)号：US09001924B1

公开(公告)日：2015-04-07

申请号：US13757084

申请日：2013-02-01

Applicant: Xilinx, Inc.

Inventor： Michael Wu ,  Bei Yin ,  Aida Vosoughi ,  Christopher H. Dick ,  Christoph E. Studer ,  Joseph R. Cavallaro

IPC: H04L27/00 ,  H04B7/04 ,  G06F17/16

CPC classification number: G06F17/16 ,  H04B7/0413

Abstract: An apparatus relating generally to matrix inversion is disclosed. This apparatus includes a matrix inversion module coupled to receive matrix information and to provide an approximation of an inversion of the matrix information. The matrix inversion module comprises a decomposition block coupled to receive the matrix information and to decompose the matrix information into diagonal matrix information and off diagonal matrix information, and an expansion block. The expansion block is coupled to receive the diagonal matrix information and the off diagonal matrix information, and to invert a matrix sum of the diagonal matrix information and the off diagonal matrix information by generation of a portion of a series expansion.

Abstract translation: 公开了一般涉及矩阵反演的装置。 该装置包括耦合以接收矩阵信息并提供矩阵信息的反演的近似的矩阵反演模块。 矩阵反演模块包括耦合以接收矩阵信息并将矩阵信息分解为对角矩阵信息和离散对角矩阵信息的分解块和扩展块。 扩展块被耦合以接收对角矩阵信息和非对角矩阵信息，并且通过生成一系列扩展的一部分来反转对角矩阵信息和非对角矩阵信息的矩阵和。

公开(公告)号：US09967057B1

公开(公告)日：2018-05-08

申请号：US15345353

申请日：2016-11-07

Applicant: Xilinx, Inc.

Inventor： Nihat E. Tunali ,  Michael Wu ,  Hai-Jo Tarn ,  Christopher H. Dick

IPC: H04L27/06 ,  H04L1/00 ,  G06F17/18

CPC classification number: H04L1/0045 ,  G06F17/10 ,  H04L25/067

Abstract: A method includes communicating data in a channel. Received symbols for the data correspond to points of a received symbol space respectively. First and second dimensions of the received symbol space correspond to a real part and an imaginary part of the received symbols respectively. A first received symbol for the data is obtained. A first region of the received symbol space for the first received symbol is determined. A first regression model associated with the first region and a first bit of the first received symbol is retrieved from a storage. The first regression model includes a plurality of regressors. A first log-likelihood ratio (LLR) for the first bit of the first received symbol is estimated using the first regression model.

公开(公告)号：US09876657B1

公开(公告)日：2018-01-23

申请号：US15451209

申请日：2017-03-06

Applicant: Xilinx, Inc.

Inventor： Charles Jeon ,  Christoph E. Studer ,  Michael Wu ,  Christopher H. Dick

IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49 ,  H04B7/0452

CPC classification number: H04L25/03159 ,  H04B7/0452 ,  H04L25/03012 ,  H04L2025/03426

Abstract: An integrated circuit (IC) includes a downlink unit including an input to receive a first plurality of frequency domain (FD) symbols associated with data symbols for a plurality of users, and an iteration unit to perform a plurality of iterations based on adjustment values. Each iteration includes generating a second plurality of FD symbols by performing a precoding process based on the first plurality of FD symbols, generating a third plurality of time domain (TD) symbols by performing a first modulation process based on the second plurality of FD symbols, generating a fourth plurality of TD symbols by performing a dynamic range reduction process based on absolute values of the third plurality of TD symbols, and updating the adjustment values. The downlink unit further includes a decision unit configured to generate transmit TD symbols for transmission through a channel to the plurality of users.

公开(公告)号：US09525470B1

公开(公告)日：2016-12-20

申请号：US14887186

申请日：2015-10-19

Applicant: Xilinx, Inc.

Inventor： Michael Wu ,  Christopher H. Dick ,  Christoph E. Studer

IPC: H04B7/04 ,  H04L5/00

CPC classification number: H04B7/0456 ,  H04B7/0452 ,  H04L5/0023

Abstract: A system includes a memory and an integrated circuit coupled to the memory. The integrated circuit is configured to communicate data in a channel characterized as a space having at least a frequency dimension. Anchor locations within the space correspond to respective regions of the space. The integrated circuit is further configured to determine a first inverse of a first matrix that corresponds to a first channel matrix for a first anchor location of the anchor locations. The first anchor location corresponds to a first region of the regions. The integrated circuit is further configured to perform an access link process for a second location other than the first anchor location but within the first region, the access link process using the first inverse determined for the first anchor location.

Abstract translation: 系统包括存储器和耦合到存储器的集成电路。 集成电路被配置为在特征为具有至少频率维度的空间的信道中传送数据。 空间内的锚定位置对应于空间的相应区域。 集成电路还被配置为确定对应于锚位置的第一锚定位置的第一信道矩阵的第一矩阵的第一逆。 第一锚定位置对应于区域的第一区域。 集成电路还被配置为对除第一锚定位置之外但在第一区域内的第二位置执行接入链路处理，该接入链路处理使用为第一锚定位置确定的第一个反相。

公开(公告)号：US11580191B1

公开(公告)日：2023-02-14

申请号：US15963234

申请日：2018-04-26

Applicant: Xilinx, Inc.

Inventor： Albert T. Gural ,  Michael Wu ,  Christopher H. Dick

IPC: G06F17/15 ,  G06N3/063 ,  G06F17/16

Abstract: Method and system relating generally to convolution is disclosed. In such a method, an image patch is selected from input data for a first channel of a plurality of input channels of an input layer. The selected image patch is transformed to obtain a transformed image patch. The transformed image patch is stored. Stored is a plurality of predetermined transformed filter kernels. A stored transformed filter kernel of the plurality of stored predetermined transformed filter kernels is element-wise multiplied by multipliers with the stored transformed image patch for a second channel of the plurality of input channels different from the first channel to obtain a product. The product is inverse transformed to obtain a filtered patch for the image patch.

公开(公告)号：US20200089472A1

公开(公告)日：2020-03-19

申请号：US16136041

申请日：2018-09-19

Applicant: Xilinx, Inc.

Inventor： Satyaprakash Pareek ,  Anup Hosangadi ,  Bing Tian ,  Ashish Sirasao ,  Yao Fu ,  Oscar Fernando C. Fernandez ,  Michael Wu ,  Christopher H. Dick

IPC: G06F7/499 ,  G06F7/544 ,  G06F9/38 ,  G06F9/30

Abstract: Circuits and method for multiplying floating point operands. An exponent adder circuit sums a first exponent and a second exponent and generates an output exponent. A mantissa multiplier circuit multiplies a first mantissa and a second mantissa and generates an output mantissa. A first conversion circuit converts the output exponent and output mantissa into a fixed point number. An accumulator circuit sums contents of an accumulation register and the fixed point number into an accumulated value and stores the accumulated value in the accumulation register.

公开(公告)号：US11704536B1

公开(公告)日：2023-07-18

申请号：US16427214

申请日：2019-05-30

Applicant: Xilinx, Inc.

Inventor： Michael Wu ,  Christopher H. Dick

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06N3/08

Abstract: Disclosed approaches for convolving input feature maps in a neural network include a circuit arrangement circuit that includes memory circuitry and convolution circuitry. The memory circuitry is configured to store K NxN first filters, and C 1x1 second filters, wherein N ≥ 1, and 1

公开(公告)号：US10747502B2

公开(公告)日：2020-08-18

申请号：US16136041

申请日：2018-09-19

Applicant: Xilinx, Inc.

Inventor： Satyaprakash Pareek ,  Anup Hosangadi ,  Bing Tian ,  Ashish Sirasao ,  Yao Fu ,  Oscar Fernando C. Fernandez ,  Michael Wu ,  Christopher H. Dick

IPC: G06F7/544 ,  G06F7/499 ,  G06F9/30 ,  G06F9/38

Abstract: Circuits and method for multiplying floating point operands. An exponent adder circuit sums a first exponent and a second exponent and generates an output exponent. A mantissa multiplier circuit multiplies a first mantissa and a second mantissa and generates an output mantissa. A first conversion circuit converts the output exponent and output mantissa into a fixed point number. An accumulator circuit sums contents of an accumulation register and the fixed point number into an accumulated value and stores the accumulated value in the accumulation register.