公开(公告)号：US10291501B1

公开(公告)日：2019-05-14

申请号：US15886688

申请日：2018-02-01

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Giovanni Guasti

IPC: G11C7/00 ,  H04L12/26 ,  G11C7/10

Abstract: An integrated circuit (IC) includes a first device and a second device. A latency measurement circuit is configured to determine a first latency of the first device; and determine a second latency of the second device based on the first latency.

公开(公告)号：US10832757B1

公开(公告)日：2020-11-10

申请号：US16279851

申请日：2019-02-19

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Giovanni Guasti

IPC: G11C8/00 ,  G11C11/4076 ,  G11C7/22 ,  G06F1/10

Abstract: A receiver implemented in an integrated circuit device is described. The receiver circuit comprises a first receiver circuit configured to receive first data, wherein the first receiver circuit comprises a first memory element configured to receive the first data in response to a first clock signal; a latency mirror circuit configured to receive second data, wherein the latency mirror circuit comprises a second memory element configured to receive the second data in response to a second clock signal; and a latency control circuit configured to detect a latency in the second data, wherein the latency control circuit adjusts a phase of the first clock signal used to receive the first data in the first receiver circuit.

公开(公告)号：US09331724B2

公开(公告)日：2016-05-03

申请号：US14486820

申请日：2014-09-15

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Giovanni Guasti

IPC: G06F3/00 ,  H04B1/04 ,  G06F1/10 ,  G06F5/06 ,  G11C7/22 ,  H04L25/05

CPC classification number: H04B1/0475 ,  G06F1/10 ,  G06F5/06 ,  G06F13/4018 ,  G06F13/423 ,  G11C7/22 ,  G11C7/222 ,  H04L25/05

Abstract: In a method relating generally to starting a plurality of transmitters, a sequence is initiated for each of the plurality of transmitters having corresponding data buffers. Latency is set for each of the data buffers responsive to execution of the sequence. The sequence includes: obtaining a read address associated with a read clock signal; obtaining a write address associated with a write clock signal; determining a difference between the read address and the write address; asserting a flag signal associated with the difference; and adjusting the read clock signal to change the difference to locate a change of state location for the flag signal to set the latency for a data buffer of the data buffers.

Abstract translation: 在一般涉及启动多个发射机的方法中，针对具有相应数据缓冲器的多个发射机中的每一个启动序列。 响应于序列的执行，为每个数据缓冲区设置延迟。 该序列包括：获得与读取时钟信号相关联的读取地址; 获得与写入时钟信号相关联的写入地址; 确定读取地址和写入地址之间的差异; 断言与差异相关联的标志信号; 并且调整读取时钟信号以改变差异以定位标志信号的状态位置的变化，以设置数据缓冲器的数据缓冲器的等待时间。

公开(公告)号：US20160080008A1

公开(公告)日：2016-03-17

申请号：US14486820

申请日：2014-09-15

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Giovanni Guasti

IPC: H04B1/04

CPC classification number: H04B1/0475 ,  G06F1/10 ,  G06F5/06 ,  G06F13/4018 ,  G06F13/423 ,  G11C7/22 ,  G11C7/222 ,  H04L25/05

Abstract: In a method relating generally to starting a plurality of transmitters, a sequence is initiated for each of the plurality of transmitters having corresponding data buffers. Latency is set for each of the data buffers responsive to execution of the sequence. The sequence includes: obtaining a read address associated with a read clock signal; obtaining a write address associated with a write clock signal; determining a difference between the read address and the write address; asserting a flag signal associated with the difference; and adjusting the read clock signal to change the difference to locate a change of state location for the flag signal to set the latency for a data buffer of the data buffers.

Abstract translation: 在一般涉及启动多个发射机的方法中，针对具有相应数据缓冲器的多个发射机中的每一个启动序列。 响应于序列的执行，为每个数据缓冲区设置延迟。 该序列包括：获得与读取时钟信号相关联的读取地址; 获得与写入时钟信号相关联的写入地址; 确定读取地址和写入地址之间的差异; 断言与差异相关联的标志信号; 并且调整读取时钟信号以改变差异以定位标志信号的状态位置的变化，以设置数据缓冲器的数据缓冲器的等待时间。