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    SYSTEM AND METHOD OF SENDING DATA VIA ADDITIONAL SECONDARY DATA LINES ON A BUS
    1.
    发明申请
    SYSTEM AND METHOD OF SENDING DATA VIA ADDITIONAL SECONDARY DATA LINES ON A BUS 审中-公开

    公开(公告)号：US20180225251A1

    公开(公告)日：2018-08-09

    申请号：US15942277

    申请日：2018-03-30

    申请人： QUALCOMM Incorporated

    发明人： Gilad Sthoeger ,  Michael Zilbershtein ,  Alexander Khazin ,  Ben Levin

    IPC分类号： G06F13/42 ,  G06F1/12

    CPC分类号： G06F13/4282 ,  G06F1/12 ,  G06F13/423 ,  G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

    摘要： A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

    BUS INTERFACE SYSTEM FOR POWER EXTRACTION
    2.
    发明申请
    BUS INTERFACE SYSTEM FOR POWER EXTRACTION 审中-公开

    公开(公告)号：US20180217959A1

    公开(公告)日：2018-08-02

    申请号：US15886209

    申请日：2018-02-01

    申请人： Qorvo US, Inc.

    发明人： Christopher Truong Ngo ,  Praveen Varma Nadimpalli ,  Alexander Wayne Hietala

    IPC分类号： G06F13/42 ,  G06F1/26 ,  G06F1/18

    CPC分类号： G06F13/423 ,  G06F1/182 ,  G06F1/189 ,  G06F1/26

    摘要： The present disclosure relates to a bus interface system including a bus line, master integrated circuitry (IC), and slave IC. The master IC is coupled to the bus line and configured to transmit the data signal to the slave IC through the bus line. The slave IC is coupled to the bus line so as to receive the data signal from the master IC and includes a supply capacitor, which is configured to store power from the data signal and provide a supply voltage to the slave IC. When the bus line is in the low state, the supply capacitor is isolated from the bus line. When the bus line is in the high state, the supply capacitor is allowed to extract power from the data signal on the bus line.

    Method and device for synchronizing a control unit and at least one assigned peripheral unit
    5.
    发明授权
    Method and device for synchronizing a control unit and at least one assigned peripheral unit 有权

    公开(公告)号：US09703749B2

    公开(公告)日：2017-07-11

    申请号：US14474975

    申请日：2014-09-02

    申请人： JOHANNES HEIDENHAIN GMBH

    发明人： Robert Wastlhuber

    IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F5/00 ,  G06F13/36 ,  G06F13/362 ,  G06F13/372 ,  G06F13/42 ,  G05B19/042

    CPC分类号： G06F13/423 ,  G05B19/0426

    摘要： In a method for synchronizing a control unit and at least one peripheral unit having actuators and/or sensors, the control unit and the peripheral unit exchange data with each other via a serial interface. The control unit transmits data to the at least one peripheral unit which is processed in the peripheral unit for the operation of the actuators and/or sensors, and at least one synchronization character is transmitted from the control unit to the peripheral unit for the synchronization. In this context, the synchronization character is appended by the control unit to a first data sequence of a data stream to be transmitted from the control unit to the peripheral unit, and the transmission of a second data sequence to be transmitted after the first data sequence is delayed in time on the part of the control unit, so that the second data sequence is transmitted by the control unit to the peripheral unit following the synchronization character.

    Techniques for inter-component communication based on a state of a chip select pin
    9.
    发明授权
    Techniques for inter-component communication based on a state of a chip select pin 有权
    基于芯片选择引脚状态的组件间通信技术

    公开(公告)号：US09588922B2

    公开(公告)日：2017-03-07

    申请号：US14668013

    申请日：2015-03-25

    申请人： Intel Corporation

    发明人： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

    IPC分类号： G06F13/00 ,  G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F13/42 ,  G06F11/07 ,  G06F11/10 ,  G06F11/22 ,  G06F13/12 ,  G06F13/40 ,  G06F11/30 ,  G06F13/16

    CPC分类号： G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

    摘要： Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

    摘要翻译： 具有组件间通信能力的分量设备和具有这种组件设备的系统在此被公开。 在实施例中，这样的组件可以包括多个控制引脚，包括时钟引脚，多个数据引脚和逻辑单元。 逻辑单元可以被配置为通过时钟引脚从另一个组件接收时钟信号，以通过所选择的一个控制和数据引脚向另一个组件提供警报信号，以启动与其他组件的交易，以便接收 通过数据引脚响应来自其他组件的警报信号，以确定事务的性质的状态请求，并且通过数据引脚向另一个组件响应状态请求来提供表示事务性质的状态。 提供警报信号，接收状态请求和提供状态可以参考时钟信号。 可以公开或要求保护其他实施例。