公开(公告)号：US09666266B1

公开(公告)日：2017-05-30

申请号：US15150115

申请日：2016-05-09

Applicant: Xilinx, Inc.

Inventor： Hongbin Ji ,  Ephrem C. Wu ,  Thomas H. Strader

IPC: G11C11/418

CPC classification number: G11C11/418 ,  G11C8/06 ,  G11C11/413 ,  G11C19/287

Abstract: In disclosed circuit arrangements, memory cell arrays are addressed by a first portion of an input address, and memory cells within each memory cell array are addressed by a second portion of the input address. A first first-in-first-out (FIFO) buffer is coupled to the memory cell arrays and delays the second portion of each input address to the memory cell arrays for a sleep period. Control circuits respectively coupled to the memory cell arrays include second FIFO buffers and decode the first portion of each input address and generate corresponding states of enable signals. The control circuits store the corresponding states of the enable signals in the second FIFO buffers concurrently with input of the second portion of each input address to the first FIFO buffer. The second FIFO buffers delay output of the corresponding states of the enable signals to the memory cell arrays for the sleep period. Each control circuit further switches a corresponding memory cell array into a sleep mode in response to all states of the enable signal in the corresponding second FIFO buffer being in a non-enabled state.

公开(公告)号：US09083340B1

公开(公告)日：2015-07-14

申请号：US14278244

申请日：2014-05-15

Applicant: Xilinx, Inc.

Inventor： Ephrem C. Wu ,  Hongbin Ji ,  Rafael C. Camarota

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1776

Abstract: An integrated circuit comprises a memory matrix including: a first memory cell array; a first multiplexer (MUX) coupled to an input of the first memory cell array; a second MUX coupled to an output of the first memory cell array; a second memory cell array; a third MUX coupled to an input of the second memory cell array; and a fourth MUX coupled to an output of the second memory cell array. The second MUX is coupled to the fourth MUX. The fourth MUX is configured to pass a selected one of: (1) an output from the third MUX, (2) an output from the second memory cell array, or (3) an output from the second MUX.

Abstract translation: 一种集成电路包括存储矩阵，其包括：第一存储单元阵列; 耦合到所述第一存储单元阵列的输入的第一多路复用器（MUX）; 耦合到所述第一存储单元阵列的输出的第二MUX; 第二存储单元阵列; 耦合到所述第二存储单元阵列的输入的第三MUX; 以及耦合到第二存储单元阵列的输出的第四MUX。 第二MUX耦合到第四MUX。 第四MUX被配置为传递以下选择的一个：（1）来自第三MUX的输出，（2）来自第二存储单元阵列的输出，或（3）来自第二MUX的输出。