公开(公告)号：US10763862B1

公开(公告)日：2020-09-01

申请号：US16285588

申请日：2019-02-26

申请人： Xilinx, Inc.

发明人： Rafael C. Camarota ,  Ui S. Han ,  Weiguang Lu

IPC分类号： H03K19/17736 ,  G06F30/33

摘要： Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements. The boundary logic interfaces are outside of a boundary of the programmable logic region. A first boundary logic interface (BLI) of the boundary logic interfaces is configured to be communicatively connected to an exterior circuit. The first BLI includes an interface configured to communicate a signal between the exterior circuit and the programmable logic region.

公开(公告)号：US20170373692A1

公开(公告)日：2017-12-28

申请号：US15191288

申请日：2016-06-23

申请人： Xilinx, Inc.

发明人： Benjamin S. Devlin ,  Rafael C. Camarota

IPC分类号： H03K19/177 ,  G01R31/3177 ,  G01R31/317

CPC分类号： H03K19/17792 ,  G01R31/31723 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318583 ,  G01R31/31937 ,  H03K19/17728 ,  H03K19/1776

摘要： A circuit for implementing a scan chain in programmable resources of an integrated circuit is described. The circuit comprises a programmable element configured to receive an input signal and generate an output signal based upon the input signal; a selection circuit configured to receive the output signal generated by the programmable element at a first input and to receive a scan chain input signal at a second input, wherein the selection circuit generates a selected output signal in response to a selection circuit control signal; and a register configured to receive the selected output signal of the selection circuit.

公开(公告)号：US10177107B2

公开(公告)日：2019-01-08

申请号：US15225550

申请日：2016-08-01

申请人： Xilinx, Inc.

发明人： Rafael C. Camarota

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/528

摘要： Methods and apparatus are described for strategically arranging conductive elements (e.g., solder balls) of an integrated circuit (IC) package (and the corresponding conductive pads of a circuit board for electrical connection with the IC package) using a plurality of different pitches. One example integrated circuit (IC) package generally includes an integrated circuit die and an arrangement of electrically conductive elements coupled to the integrated circuit die. In at least one region of the arrangement, the conductive elements are disposed with a first pitch in a first dimension of the arrangement and with a second pitch in a second dimension of the arrangement, and the second pitch is different from the first pitch. The pitch of a given region may be based on mechanical, PCB routing, and/or signal integrity considerations.

公开(公告)号：US08913455B1

公开(公告)日：2014-12-16

申请号：US13953390

申请日：2013-07-29

申请人： Xilinx, Inc.

发明人： Rafael C. Camarota

IPC分类号： G11C8/00 ,  G11C7/10 ,  G11C11/00 ,  H01L21/8238 ,  G11C11/412

CPC分类号： H01L21/8238 ,  G11C8/16 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/785

摘要： A multi-port memory cell is disclosed that includes first and second cross-coupled inverter circuits. The input node of each inverter circuit is coupled to the output node of the other inverter circuit to receive the inverted output of the other inverter circuit. The multi-port memory cell includes a first pair of access transistors of a first type, each coupled to the input node of a respective one of the first and second inverter circuits. The multi-port memory cell also includes a second pair of access transistors of the second type, each coupled to the input of a respective one of the first and second inverter circuits. The multi-port cell exhibits advantages in layout compactness and SEU tolerance.

摘要翻译： 公开了一种包括第一和第二交叉耦合的反相器电路的多端口存储单元。 每个逆变器电路的输入节点耦合到另一个逆变器电路的输出节点，以接收另一个逆变器电路的反相输出。 多端口存储单元包括第一类型的第一对存取晶体管，每一个都连接到第一和第二反相器电路中的相应一个的输入节点。 多端口存储单元还包括第二类型的第二对存取晶体管，每一个都连接到第一和第二反相器电路中的相应一个的输入端。 多端口电池在布局紧凑性和SEU容差方面具有优势。

公开(公告)号：US11189338B1

公开(公告)日：2021-11-30

申请号：US16833043

申请日：2020-03-27

申请人： XILINX, INC.

发明人： Rafael C. Camarota

IPC分类号： G11C5/02 ,  G11C11/4096 ,  H01L23/00 ,  H01L23/14 ,  H01L23/538 ,  H01L25/18

摘要： Certain aspects of the present disclosure provide techniques for relate to electronic devices that are configured to implement multi-rank high bandwidth memory (HBM) memory. In one aspect, an electronic device includes a chip that includes an interface circuit. The interface circuit is connected to first exterior pads. The first exterior pads have a first number of first data input/output exterior pads and a second number of clock enable output exterior pads. The first number is a first integer multiple of a number of data signals per channel of high bandwidth memory (HBM), and the second number is a second integer multiple of a number of clock enable signals per channel of the HBM. The second integer multiple is greater than the first integer multiple.

公开(公告)号：US11169822B2

公开(公告)日：2021-11-09

申请号：US16276178

申请日：2019-02-14

申请人： Xilinx, Inc.

发明人： Rafael C. Camarota ,  David P. Schultz

IPC分类号： G06F9/445 ,  G06F13/40

摘要： Examples described herein provide for an integrated circuit (IC) having a programmable logic region that is capable of being configured via a programmable network. In an example, an IC includes a programmable logic region, a controller, and a programmable network. The programmable network is connected between the controller and the programmable logic region. The controller is programmed to configure the programmable logic region via the programmable network. In some examples, the programmable logic region can be configured faster, among other benefits.

公开(公告)号：US10963411B1

公开(公告)日：2021-03-30

申请号：US16502141

申请日：2019-07-03

申请人： XILINX, INC.

发明人： Martin L. Voogel ,  Trevor J. Bauer ,  Rafael C. Camarota

IPC分类号： G06F13/40 ,  G06F13/20 ,  G06F13/16 ,  G06F13/12 ,  H03M1/12

摘要： Programmable devices and methods of operation are disclosed. In some embodiments, a programmable device may include programmable logic selectively coupled to a plurality of input/output (I/O) interface circuits by a programmable interconnect fabric and a network-on-chip (NoC) interconnect system. The programmable logic may include configurable logic elements, programmable interconnects, and dedicated circuitry. The programmable interconnects may form part of the programmable interconnect fabric. In some embodiments, the programmable interconnect fabric selectively routes non-packetized data between the programmable logic and a first group of I/O interface circuits, and the NoC interconnect system selectively routes packetized data between the programmable logic and a second group of I/O interface circuits. The NoC interconnect system may operate according to a data packet protocol, and the second group of I/O interface circuits may include memory controllers compatible with the data packet protocol.

公开(公告)号：US09911465B1

公开(公告)日：2018-03-06

申请号：US15346512

申请日：2016-11-08

申请人： Xilinx, Inc.

发明人： Rafael C. Camarota ,  Sagheer Ahmad ,  Martin Newman

IPC分类号： G11C5/02 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/78 ,  H01L21/56 ,  H01L25/00 ,  G11C5/06

CPC分类号： G11C5/025 ,  G11C5/06 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2924/15192

摘要： Methods and apparatus are described for adding one or more features (e.g., HBM) to a qualified SSI technology programmable IC region by providing an interface (e.g., an HBM buffer region with a switch network) between the added feature device and the programmable IC region. One example IC package generally includes a package substrate; at least one interposer disposed above the package substrate; a programmable IC region disposed above the interposer; at least one fixed feature die disposed above the interposer; and an interface region disposed above the interposer and configured to couple the programmable IC region to the fixed feature die via a first set of interconnection lines routed through the interposer between a first plurality of ports of the interface region and the fixed feature die and a second set of interconnection lines routed between a second plurality of ports of the interface region and the programmable IC region.

公开(公告)号：US20180047663A1

公开(公告)日：2018-02-15

申请号：US15237384

申请日：2016-08-15

申请人： Xilinx, Inc.

发明人： Rafael C. Camarota

IPC分类号： H01L23/498 ,  H01L23/528 ,  H01L21/48 ,  H01L21/78 ,  H01L21/56 ,  H01L25/065 ,  H01L23/544 ,  H01L25/00

摘要： Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to an existing qualified stacked silicon interconnect (SSI) technology programmable IC die (e.g., a super logic region (SLR)) without changing the programmable IC die (e.g., adding or removing blocks). One example integrated circuit (IC) package generally includes a package substrate; at least one interposer disposed above the package substrate and comprising a plurality of interconnection lines; a programmable IC die disposed above the interposer; a fixed feature die disposed above the interposer; and an interface die disposed above the interposer and configured to couple the programmable IC die to the fixed feature die using a first set of interconnection lines routed through the interposer between the programmable IC die and the interface die and a second set of interconnection lines routed through the interposer between the interface die and the fixed feature die.

公开(公告)号：US09204542B1

公开(公告)日：2015-12-01

申请号：US13735338

申请日：2013-01-07

申请人： Xilinx, Inc.

发明人： Tien-Yu Lee ,  Rafael C. Camarota

IPC分类号： H05K1/11 ,  G06F17/50

CPC分类号： H05K1/111 ,  G06F17/5054 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/40 ,  H01L25/0655 ,  H01L2224/16227

摘要： An apparatus includes a package substrate for a first SSIT product with a first top die configuration, wherein the package substrate is compatible with a second SSIT product with a second top die configuration, and wherein the first top die configuration is different from the second top die configuration.

摘要翻译： 一种装置包括用于具有第一顶模配置的第一SSIT产品的封装衬底，其中所述封装衬底与具有第二顶模配置的第二SSIT产品兼容，并且其中所述第一顶模配置不同于所述第二顶模 组态。