公开(公告)号：US10126361B1

公开(公告)日：2018-11-13

申请号：US15351085

申请日：2016-11-14

Applicant: Xilinx, Inc.

Inventor： Xiaojian Yang ,  Maogang Wang ,  Grigor S. Gasparyan ,  Raoul Badaoui

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

Abstract: Processing a circuit design that specifies application logic and debugging logic includes partitioning the circuit design. Each partition includes a part of the application logic and a part of the debugging logic, each partition is specified for implementation on a respective IC die, and the circuit design specifies connections between a part of the application logic in one partition and a part of the debugging logic in another partition. The connections between the part of the application logic in the one partition and the part of the debugging logic in the other partition are changed to connections from the part of the application logic in the one partition to a part of the debugging logic in the one partition. The part of the application logic and the part of the debugging logic of each partition are placed and routed on the respective IC die.