公开(公告)号：US10126361B1

公开(公告)日：2018-11-13

申请号：US15351085

申请日：2016-11-14

Applicant: Xilinx, Inc.

Inventor： Xiaojian Yang ,  Maogang Wang ,  Grigor S. Gasparyan ,  Raoul Badaoui

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

Abstract: Processing a circuit design that specifies application logic and debugging logic includes partitioning the circuit design. Each partition includes a part of the application logic and a part of the debugging logic, each partition is specified for implementation on a respective IC die, and the circuit design specifies connections between a part of the application logic in one partition and a part of the debugging logic in another partition. The connections between the part of the application logic in the one partition and the part of the debugging logic in the other partition are changed to connections from the part of the application logic in the one partition to a part of the debugging logic in the one partition. The part of the application logic and the part of the debugging logic of each partition are placed and routed on the respective IC die.

公开(公告)号：US10042971B1

公开(公告)日：2018-08-07

申请号：US15210756

申请日：2016-07-14

Applicant: Xilinx, Inc.

Inventor： Mehrdad Eslami Dehkordi ,  Raoul Badaoui ,  Marvin Tom ,  Sridhar Krishnamurthy

IPC: G06F17/50

Abstract: Approaches for routing clock signals of a circuit design on an IC include determining initial partitions of clock sources and clock loads. Each initial partition includes one of the clock sources and a subset of the clock loads associated with the one clock source, and initial each partition defines an area of the IC in which the one of the clock sources and the associated subset of clock loads are placed. A processor determines for each of the initial partitions, whether or not the initial partition has a congested clock region. For each initial partition determined to have a congested clock region, the processor defines a respective new partition by excluding the one of the clock sources from the new partition. The new partition includes the subset of the clock loads and does not include the one clock source. The processor then routes clock signals from the clock sources to the clock loads.