公开(公告)号：US10860765B1

公开(公告)日：2020-12-08

申请号：US16283552

申请日：2019-02-22

Applicant: Xilinx, Inc.

Inventor： Wuxi Li ,  Mehrdad Eslami Dehkordi ,  Xiaojian Yang

IPC: G06F17/50 ,  G06F30/34 ,  H03K19/17736 ,  G06F30/396

Abstract: Some examples described herein provide for clock tree generation for a programmable logic device, and more specifically, for clock tree generation in conjunction or simultaneous with placement of logic for a programmable logic device. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to: generate clock trees in conjunction with placing logic for an application to be implemented in a programmable logic region of a programmable logic device; generate data routes between the placed logic; and generate a physical implementation of the application based on the placed logic, the clock trees, and the data routes. The physical implementation is capable of being loaded on the programmable logic region of the programmable logic device.

公开(公告)号：US12019964B1

公开(公告)日：2024-06-25

申请号：US17376892

申请日：2021-07-15

Applicant: Xilinx, Inc.

Inventor： Karthic P ,  Paul Kundarewich ,  Satish Sivaswamy ,  Meghraj Kalase ,  Vishal Tripathi ,  Srinivasan Dasasathyan ,  Mehrdad Eslami Dehkordi ,  Xiaojian Yang ,  Amish Pandya

IPC: G06F30/337 ,  G06F30/392 ,  G06N20/00

CPC classification number: G06F30/337 ,  G06F30/392 ,  G06N20/00

Abstract: Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the first range of runtimes. The implementation flow is executed by the design tool in a plurality of processes in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the second range of runtimes.

公开(公告)号：US10242150B1

公开(公告)日：2019-03-26

申请号：US15175897

申请日：2016-06-07

Applicant: Xilinx, Inc.

Inventor： Sabyasachi Das ,  Xiaojian Yang ,  Niyati Shah ,  Govinda Keshavdas ,  Frederic Revenu

IPC: G06F17/50

Abstract: Circuit design implementation can include selecting a first and second load each having a control pin of a same type driven by a different driver, determining whether the driver of the first load matches the driver of the second load, and modifying the circuit design to drive the control pins of the first load and the second load using the driver of the first load. Circuit design implementation can include selecting a net having a driver and a plurality of loads exceeding a threshold, determining a selected module of the circuit design having a number of the plurality of loads of the net that meet a cloning criteria, and, in response, modifying the circuit design by creating a clone of the driver within the selected module and driving each load of the net within the selected module with the clone of the driver.

公开(公告)号：US10108773B1

公开(公告)日：2018-10-23

申请号：US15350957

申请日：2016-11-14

Applicant: Xilinx, Inc.

Inventor： Grigor S. Gasparyan ,  Xiao Dong ,  Xiaojian Yang

IPC: G06F17/50

Abstract: Partitioning a circuit design can include determining, using a processor, a target area utilization and a target cut utilization by iterating over a range of timing violations and determining, using the processor, a worst allowed timing violation based upon the target area utilization and the target cut utilization. Circuit elements of the circuit design can be assigned to partitions, using the processor, for implementation of the circuit design in a multi-die integrated circuit based upon a partition cost calculated using the target area utilization, the target cut utilization, and the worst allowed timing violation.

公开(公告)号：US10126361B1

公开(公告)日：2018-11-13

申请号：US15351085

申请日：2016-11-14

Applicant: Xilinx, Inc.

Inventor： Xiaojian Yang ,  Maogang Wang ,  Grigor S. Gasparyan ,  Raoul Badaoui

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

Abstract: Processing a circuit design that specifies application logic and debugging logic includes partitioning the circuit design. Each partition includes a part of the application logic and a part of the debugging logic, each partition is specified for implementation on a respective IC die, and the circuit design specifies connections between a part of the application logic in one partition and a part of the debugging logic in another partition. The connections between the part of the application logic in the one partition and the part of the debugging logic in the other partition are changed to connections from the part of the application logic in the one partition to a part of the debugging logic in the one partition. The part of the application logic and the part of the debugging logic of each partition are placed and routed on the respective IC die.

公开(公告)号：US11681846B1

公开(公告)日：2023-06-20

申请号：US17147163

申请日：2021-01-12

Applicant: XILINX, INC.

Inventor： Xiaojian Yang ,  Frederic Revenu ,  Dinesh D. Gaitonde ,  Amit Gupta

IPC: G06F30/343 ,  G06F30/347

CPC classification number: G06F30/343 ,  G06F30/347

Abstract: A method of FPGA compilation for an emulation system includes receiving a netlist for an FPGA, partitioning the netlist into a set of sub-FPGA netlists, and mapping each of the sub-FPGA netlists in the set to a corresponding dynamic sub-FPGA region of the FPGA. The method further includes implementing the sub-FPGA netlists of the set in parallel to obtain a corresponding set of sub-FPGA bitstreams.

公开(公告)号：US10956638B1

公开(公告)日：2021-03-23

申请号：US16514324

申请日：2019-07-17

Applicant: XILINX, INC.

Inventor： Bart Reynolds ,  Xiaojian Yang ,  Matthew H. Klein

IPC: G06F30/331 ,  G06F30/392 ,  G06F30/398

Abstract: Methods and apparatus are described for providing and using programmable ICs suitable for meeting the unique desires of large hardware emulation systems. One example method of classifying a programmable IC having impaired circuitry generally includes determining a partitioning of programmable logic resources into two or more groups for classifying the programmable IC, testing the programmable IC to determine at least one location of the impaired circuitry in the programmable logic resources of the programmable IC, and classifying the programmable IC based on the at least one location of the impaired circuitry in relation to the partitioning of the programmable logic resources.

公开(公告)号：US10528697B1

公开(公告)日：2020-01-07

申请号：US15818436

申请日：2017-11-20

Applicant: Xilinx, Inc.

Inventor： Wei Chen ,  Xiaojian Yang ,  Sabyasachi Das

IPC: G06F17/50

Abstract: Embodiments disclosed herein describe techniques for moving nets between a source and a plurality of sinks in a design of an integrated circuit from a data network to a clock network. In one embodiment, the clock network propagates clock signals or timing signals throughout the integrated circuit while the data network transmits data signals between circuitry in the integrated circuit. In one embodiment, the clock network has a predefined number of clock signal nets which can be assigned to carry clock signals to circuit logic in the integrated circuit. However, some of the clock signal nets may be unused. In one embodiment, a design application identifies candidate sinks which have positive slack. If using the clock network to couple the sink to the source satisfies predetermined timing requirements, then the design change is committed.

公开(公告)号：US10402521B1

公开(公告)日：2019-09-03

申请号：US15410597

申请日：2017-01-19

Applicant: Xilinx, Inc.

Inventor： Bart Reynolds ,  Xiaojian Yang ,  Matthew H. Klein

IPC: G06F17/50

Abstract: Methods and apparatus are described for providing and using programmable ICs suitable for meeting the unique desires of large hardware emulation systems. One example method of classifying a programmable IC having impaired circuitry generally includes determining a partitioning of programmable logic resources into two or more groups for classifying the programmable IC, testing the programmable IC to determine at least one location of the impaired circuitry in the programmable logic resources of the programmable IC, and classifying the programmable IC based on the at least one location of the impaired circuitry in relation to the partitioning of the programmable logic resources.