公开(公告)号：US20240311541A1

公开(公告)日：2024-09-19

申请号：US18184923

申请日：2023-03-16

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Padala V Santhosh ,  Srinivasan Dasasathyan

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: Preplacement clock resolution for implementing a circuit design includes, prior to placement of the circuit design, determining, using computer hardware, pairs of clocks of the circuit design that clock synchronous inter-clock data paths. Using the computer hardware, a clock group is generated that includes clocks having a common ancestor clock node from the pairs of clocks. A clock delay group property is set, using the computer hardware, for the clocks of the clock group prior to placement. A placed version of the circuit design is generated using the computer hardware. The circuit design is placed using the clock delay group property as set for the clocks of the clock group.