利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

856 条记录 (耗时 0.036 秒)

    Dual read port latch array bitcell
    1.
    发明授权
    Dual read port latch array bitcell 有权

    公开(公告)号：US12073919B2

    公开(公告)日：2024-08-27

    申请号：US17359445

    申请日：2021-06-25

    申请人： Advanced Micro Devices, Inc.

    发明人： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

    IPC分类号： G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

    CPC分类号： G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

    摘要： An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. A dual read port and single write port memory bit cell uses two asymmetrical read access circuits for conveying stored data on two read bit lines. The two read bit lines are pre-charged to different voltage reference levels. The layout of the memory bit cell places the two read bit lines on an opposed edge from the single write bit line. The layout uses a dummy gate placed over both p-type diffusion and n-type diffusion between the edges. The layout has a same number of p-type transistors as n-type transistors despite using asymmetrical read access circuits. The layout also has a contacted gate pitch that is one more than the number of p-type transistors.

    Standard cell design
    3.
    发明授权
    Standard cell design 有权

    公开(公告)号：US12073165B2

    公开(公告)日：2024-08-27

    申请号：US17476615

    申请日：2021-09-16

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Shu-Wei Chung ,  Tung-Heng Hsieh ,  Chung-Hui Chen ,  Chung-Yi Lin

    IPC分类号： G06F30/30 ,  G06F30/323 ,  G06F30/392 ,  G06F30/398 ,  G06F111/20

    CPC分类号： G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F2111/20

    摘要： An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    8.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240265188A1

    公开(公告)日：2024-08-08

    申请号：US18641386

    申请日：2024-04-21

    申请人： Samsung Electronics Co., Ltd.

    发明人： YONGDEOK KIM ,  MUNJUN SEO ,  Bonghyun Lee

    IPC分类号： G06F30/3953 ,  G03F1/36 ,  G06F30/392 ,  G06F30/398

    CPC分类号： G06F30/3953 ,  G03F1/36 ,  G06F30/392 ,  G06F30/398

    摘要： Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.