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    ALIGNMENT OF MACROS BASED ON ANCHOR LOCATIONS
    2.
    发明公开
    ALIGNMENT OF MACROS BASED ON ANCHOR LOCATIONS 审中-公开

    公开(公告)号：US20240193341A1

    公开(公告)日：2024-06-13

    申请号：US18078540

    申请日：2022-12-09

    Applicant: Xilinx, Inc.

    Inventor： Veeresh Pratap Singh ,  Mohit Sharma ,  Chatla Surya Phanindra ,  Sandip Maity ,  Aman Gayasen ,  Srinivasan Dasasathyan

    IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394

    CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/394

    Abstract: Placement of macros of a circuit design includes mapping the macros to types of sub-circuits of an integrated circuit (IC). The IC includes anchors and instances of each type of the types of sub-circuits. The macros are grouped based on couplings of the macros to the anchors specified in the circuit design. Each group includes one or more macros, and the one or more macros in each group are all coupled to the same set of one or more anchors. A location is selected from alternative locations for each group of macros based on a distance of the location from the same set of anchors. Each location includes one or more instances of one or more types of the types of sub-circuits. The circuit design is placed and routed after selecting the location for each group, and implementation data is generated for making an IC that implements the circuit design.

    Automated analysis and optimization of circuit designs
    3.
    发明授权
    Automated analysis and optimization of circuit designs 有权

    公开(公告)号：US11003826B1

    公开(公告)日：2021-05-11

    申请号：US16397501

    申请日：2019-04-29

    Applicant: Xilinx, Inc.

    Inventor： Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Vishal Tripathy ,  Vikas N. Vedamurthy ,  Sumit Nagpal

    IPC: G06F30/392 ,  G06F30/327 ,  G06F111/04

    Abstract: Strategies are stored in a memory arrangement, and each strategy includes a set of parameter settings for a design tool. The design tool identifies a set of features of an input circuit design and applies classification models to the input circuit design. Each classification model indicates one the strategies, and application of each classification model indicates a likelihood that use of the strategy would improve a metric of the input circuit design based on the set of features of the input circuit design. One strategy of the plurality of strategies is selected based on the likelihood that use of the one strategy would improve the metric of the input circuit design, and the design tool is configured with the set of parameter settings of the one strategy. The design tool then processes the input circuit design into implementation data that is suitable for making an integrated circuit (IC).

    Testing critical paths of a circuit design
    4.
    发明授权
    Testing critical paths of a circuit design 有权
    测试电路设计的关键路径

    公开(公告)号：US09501604B1

    公开(公告)日：2016-11-22

    申请号：US14493750

    申请日：2014-09-23

    Applicant: Xilinx, Inc.

    Inventor： Geetesh More ,  Srinivasan Dasasathyan ,  Nagaraj Savithri

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F17/5027 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2217/84

    Abstract: A method of testing a circuit design includes generating, for each net of each critical path in the circuit design, a respective ring oscillator circuit design. The ring oscillator circuit design has a source gate coupled to a destination gate via the net and a feedback path that couples an output pin of the destination gate to an input pin of the source gate. Configuration data are generated to implement a respective ring oscillator circuit from each ring oscillator circuit design, and a programmable integrated circuit is configured with the configuration data. The method determines a delay of the net of each ring oscillator circuit.

    Abstract translation: 一种测试电路设计的方法包括为电路设计中的每个关键路径的每个网络产生相应的环形振荡器电路设计。 环形振荡器电路设计具有经由网络耦合到目的地门的源极和将目的地门的输出引脚耦合到源极栅极的输入引脚的反馈路径。 生成配置数据以实现来自每个环形振荡器电路设计的相应环形振荡器电路，并且可编程集成电路被配置有配置数据。 该方法确定每个环形振荡器电路的网络的延迟。

    SATISFYING CIRCUIT DESIGN CONSTRAINTS USING A COMBINATION OF MACHINE LEARNING MODELS
    6.
    发明公开
    SATISFYING CIRCUIT DESIGN CONSTRAINTS USING A COMBINATION OF MACHINE LEARNING MODELS 审中-公开

    公开(公告)号：US20240111932A1

    公开(公告)日：2024-04-04

    申请号：US17959038

    申请日：2022-10-03

    Applicant: Xilinx, Inc.

    Inventor： Satish Bachina ,  Karthic P ,  Vishal Tripathi ,  Srinivasan Dasasathyan

    IPC: G06F30/32

    CPC classification number: G06F30/32 ,  G06F2119/06

    Abstract: Multiple classifier models are applied to features of a circuit design after processing the design through a first phase of an implementation flow. Each classifier model is associated with one of multiple directives, the directives are associated with a second phase of the implementation flow, and each classifier model returns a value indicative of likelihood of improving a quality metric. Regressor models of each set of a plurality of sets of regressor models are applied to the features. Each directive is associated with one of the sets of regressor models, and a combined score from each set of regressor models indicates a likelihood of satisfying a constraint. The directives are ranked based on the values indicated by the classifier models and scores from the sets of regressor models, and the circuit design is processed n the second phase of the implementation flow by the design tool using the directive having the highest rank.

    Visualization of data buses in circuit designs
    7.
    发明授权
    Visualization of data buses in circuit designs 有权

    公开(公告)号：US11586791B1

    公开(公告)日：2023-02-21

    申请号：US17480389

    申请日：2021-09-21

    Applicant: Xilinx, Inc.

    Inventor： Anup Hosangadi ,  Aman Gayasen ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan

    IPC: G06F30/31 ,  G06F30/394

    Abstract: Approaches for visualizing data buses in a circuit design include determining ones of the data buses that satisfy selection criteria. For each element connected to a data bus of the ones of the data buses, a method and system determine whether the element is of interest or the element is not of interest. A graphical representation of the ones of the data buses and each element of interest is generated, and data buses of the circuit design determined to not satisfy the selection criteria and elements not of interest are excluded from the graphical representation. The graphical representation is displayed on a display device.

    PRE-PLACEMENT CLOCKING IDENTIFICATION AND RESOLUTION FOR CIRCUIT DESIGNS
    8.
    发明公开
    PRE-PLACEMENT CLOCKING IDENTIFICATION AND RESOLUTION FOR CIRCUIT DESIGNS 审中-公开

    公开(公告)号：US20240311541A1

    公开(公告)日：2024-09-19

    申请号：US18184923

    申请日：2023-03-16

    Applicant: Xilinx, Inc.

    Inventor： Veeresh Pratap Singh ,  Padala V Santhosh ,  Srinivasan Dasasathyan

    IPC: G06F30/392

    CPC classification number: G06F30/392

    Abstract: Preplacement clock resolution for implementing a circuit design includes, prior to placement of the circuit design, determining, using computer hardware, pairs of clocks of the circuit design that clock synchronous inter-clock data paths. Using the computer hardware, a clock group is generated that includes clocks having a common ancestor clock node from the pairs of clocks. A clock delay group property is set, using the computer hardware, for the clocks of the clock group prior to placement. A placed version of the circuit design is generated using the computer hardware. The circuit design is placed using the clock delay group property as set for the clocks of the clock group.

    AUTOMATED TIMING CLOSURE ON CIRCUIT DESIGNS
    10.
    发明申请
    AUTOMATED TIMING CLOSURE ON CIRCUIT DESIGNS 有权

    公开(公告)号：US20230034736A1

    公开(公告)日：2023-02-02

    申请号：US17382621

    申请日：2021-07-22

    Applicant: Xilinx, Inc.

    Inventor： Veeresh Pratap Singh ,  Meghraj Kalase ,  John Blaine ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Frederic Revenu ,  Veena Johar ,  Pawan Kumar Singh ,  Mohit Sharma ,  Kameshwar Chandrasekar

    IPC: G06F30/398 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392

    Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.

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