公开(公告)号：US20180203956A1

公开(公告)日：2018-07-19

申请号：US15407875

申请日：2017-01-17

Applicant: Xilinx, Inc.

Inventor： Aaron Ng ,  Sabyasachi Das ,  Prabal Basu

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84

Abstract: Physical synthesis for a circuit design can include determining, using a processor, features relating to a signal path of the circuit design not meeting a timing requirement, processing the features through a first neural network model using the processor, wherein the first neural network model is trained to indicate effectiveness of a first physical synthesis optimization, and selectively performing, using the processor, the first physical synthesis optimization for the signal path based upon a result from the first neural network model.

公开(公告)号：US10192016B2

公开(公告)日：2019-01-29

申请号：US15407875

申请日：2017-01-17

Applicant: Xilinx, Inc.

Inventor： Aaron Ng ,  Sabyasachi Das ,  Prabal Basu

IPC: G06F17/50

Abstract: Physical synthesis for a circuit design can include determining, using a processor, features relating to a signal path of the circuit design not meeting a timing requirement, processing the features through a first neural network model using the processor, wherein the first neural network model is trained to indicate an effectiveness of a first physical synthesis optimization, and selectively performing, using the processor, the first physical synthesis optimization for the signal path based upon a result from the first neural network model.