中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.025 seconds)

    Timing optimization of memory blocks in a programmable IC
    1.
    发明授权
    Timing optimization of memory blocks in a programmable IC 有权

    公开(公告)号：US10699053B1

    公开(公告)日：2020-06-30

    申请号：US15873724

    申请日：2018-01-17

    Applicant: Xilinx, Inc.

    Inventor： Zhiyong Wang ,  Ruibing Lu ,  Lin Chai ,  Sabyasachi Das

    IPC: G06F30/398 ,  G06F30/34 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3312 ,  G06F30/39 ,  G06F30/327 ,  G06F119/12

    Abstract: Methods and apparatus for implementing a circuit design are provided. A physical description is generated corresponding to a predefined physical layout of a programmable integrated circuit. The circuit design includes a memory block. A timing analysis is executed to determine a first timing profile of the physical description. The physical description is optimized (or at least altered), and a physical implementation is generated based on the optimized physical description. Optimizing the physical description includes: selectively moving from or into the memory block of the physical description a register in response to an attribute of the memory block; executing a timing analysis to determine a second timing profile of the physical description with the register moved from or into the memory block of the physical description; comparing the first and second timing profiles; and selectively accepting or reversing the moving based on the comparison of the first and second timing profiles.

    Timing-closure methodology involving clock network in hardware designs
    2.
    发明授权
    Timing-closure methodology involving clock network in hardware designs 有权

    公开(公告)号：US10528697B1

    公开(公告)日：2020-01-07

    申请号：US15818436

    申请日：2017-11-20

    Applicant: Xilinx, Inc.

    Inventor： Wei Chen ,  Xiaojian Yang ,  Sabyasachi Das

    IPC: G06F17/50

    Abstract: Embodiments disclosed herein describe techniques for moving nets between a source and a plurality of sinks in a design of an integrated circuit from a data network to a clock network. In one embodiment, the clock network propagates clock signals or timing signals throughout the integrated circuit while the data network transmits data signals between circuitry in the integrated circuit. In one embodiment, the clock network has a predefined number of clock signal nets which can be assigned to carry clock signals to circuit logic in the integrated circuit. However, some of the clock signal nets may be unused. In one embodiment, a design application identifies candidate sinks which have positive slack. If using the clock network to couple the sink to the source satisfies predetermined timing requirements, then the design change is committed.

    Physical optimization for timing closure for an integrated circuit
    4.
    发明授权
    Physical optimization for timing closure for an integrated circuit 有权
    用于集成电路的时序闭合的物理优化

    公开(公告)号：US08984462B1

    公开(公告)日：2015-03-17

    申请号：US14249601

    申请日：2014-04-10

    Applicant: Xilinx, Inc.

    Inventor： Sabyasachi Das ,  Ruibing Lu ,  Zhiyong Wang ,  Aman Gayasen

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F2217/84

    Abstract: Physical optimization for timing closure for an integrated circuit includes processing a circuit design at least partially through a design flow to a late stage of the design flow. Using a processor, a baseline delay is calculated for each of a plurality of paths of the circuit design. A slack for each of the plurality of paths is determined. Physical optimization further includes selecting a path of the circuit design that meets a selection criterion according, at least in part, to the slack of the path, applying, using the processor, a physical optimization to the selected path resulting in an optimized path, and calculating a delay of the optimized path. The optimized path is incorporated into the circuit design only responsive to determining that the delay of the optimized path is less than the baseline delay of the selected path.

    Abstract translation: 用于集成电路的时序闭合的物理优化包括至少部分地通过设计流处理电路设计到设计流程的后期阶段。 使用处理器，为电路设计的多个路径中的每一个计算基线延迟。 确定多个路径中的每一个的松弛。 物理优化进一步包括至少部分地根据路径的松弛来选择满足选择标准的电路设计的路径，使用处理器对所选择的路径应用物理优化，得到优化的路径，以及 计算优化路径的延迟。 优化的路径被合并到电路设计中，仅响应于确定优化路径的延迟小于所选路径的基线延迟。

    Neural network based physical synthesis for circuit designs
    6.
    发明授权
    Neural network based physical synthesis for circuit designs 有权

    公开(公告)号：US10192016B2

    公开(公告)日：2019-01-29

    申请号：US15407875

    申请日：2017-01-17

    Applicant: Xilinx, Inc.

    Inventor： Aaron Ng ,  Sabyasachi Das ,  Prabal Basu

    IPC: G06F17/50

    Abstract: Physical synthesis for a circuit design can include determining, using a processor, features relating to a signal path of the circuit design not meeting a timing requirement, processing the features through a first neural network model using the processor, wherein the first neural network model is trained to indicate an effectiveness of a first physical synthesis optimization, and selectively performing, using the processor, the first physical synthesis optimization for the signal path based upon a result from the first neural network model.

    INTERACTIVE MULTI-STEP PHYSICAL SYNTHESIS
    8.
    发明申请
    INTERACTIVE MULTI-STEP PHYSICAL SYNTHESIS 有权

    公开(公告)号：US20170098024A1

    公开(公告)日：2017-04-06

    申请号：US14873072

    申请日：2015-10-01

    Applicant: Xilinx, Inc.

    Inventor： Rajat Aggarwal ,  Zhiyong Wang ,  Ruibing Lu ,  Sabyasachi Das

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84

    Abstract: A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.

    Opportunistic candidate path selection during physical optimization of a circuit design for an IC
    9.
    发明授权
    Opportunistic candidate path selection during physical optimization of a circuit design for an IC 有权
    用于IC的电路设计的物理优化期间的机会候选路径选择

    公开(公告)号：US09483597B1

    公开(公告)日：2016-11-01

    申请号：US14667324

    申请日：2015-03-24

    Applicant: Xilinx, Inc.

    Inventor： Sabyasachi Das ,  Ruibing Lu ,  Zhiyong Wang

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F17/5031 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/84

    Abstract: In an example, a method of implementing a circuit design for an integrated circuit (IC) includes: placing and routing a logical description of the circuit design to generate a physical description having a plurality of paths, and executing a timing analysis to determine a timing profile of the physical description. The method further includes optimizing the physical description by performing a plurality of iterations of: comparing the timing profile with a timing constraint to select a candidate set of paths having negative slack from the plurality of paths in the physical description; and modifying the physical description based on at least one optimization of a selected path from the candidate set of paths having a most negative slack. The method further includes generating a physical implementation of the circuit design for the IC based on the physical description.

    Abstract translation: 在一个示例中，实现集成电路（IC）的电路设计的方法包括：放置和布线电路设计的逻辑描述以产生具有多个路径的物理描述，并且执行定时分析以确定时序 档案的物理描述。 该方法还包括通过执行多个迭代来优化物理描述：将定时简档与定时约束进行比较，以在物理描述中选择具有来自多个路径的负松弛的候选路径集合; 以及基于来自具有最负的松弛的路径的候选组的所选路径的至少一个优化来修改所述物理描述。 该方法还包括基于物理描述生成用于IC的电路设计的物理实现。

    Automated pipeline insertion on a bus
    10.
    发明授权
    Automated pipeline insertion on a bus 有权

    公开(公告)号：US10970446B1

    公开(公告)日：2021-04-06

    申请号：US15988448

    申请日：2018-05-24

    Applicant: Xilinx, Inc.

    Inventor： Jeffrey H. Seltzer ,  Khang K. Dao ,  Sabyasachi Das

    IPC: G06F30/3312 ,  G06F30/34 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F119/12

    Abstract: The disclosed approaches process a circuit design having first attributes associated with two or more signals or with sources of the two or more signals. The first attributes specify identifier values. The elements of the circuit design are placed on a target integrated circuit (IC), and timing analysis of the circuit design is performed after placing the elements of the circuit design. In response to the first attributes of the two or more signals or sources specifying equivalent identifier values and a path of at least one of the two or more signals or sources being timing-critical, equal numbers of one or more pipeline registers are inserted on paths of the two or more signals or sources.

Patent Agency Ranking